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参数资料
| 型号： | TSPC603RMAB/Q6LC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 166 MHz, RISC PROCESSOR, CQFP240 |
| 封装： | CERQUAD-240 |
| 文件页数： | 7/40页 |
| 文件大小： | 670K |
| 代理商： | TSPC603RMAB/Q6LC |
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TSPC603r
in CERQUAD and MQUAD Packages
15/40
D PLL may be disabled and SYSCLK may be removed while in sleep mode.
D Return to full-power mode after PLL and SYSCLK disabled in sleep mode :
- Enable SYSCLK.
- Reconfigure PLL into desired processor clock mode.
- System logic waits for PLL startup and relock time (100
msec).
- System logic asserts one of the sleep recovery signals (for example, INT or SMI).
3.6.4. Power Management Software Considerations
Since the 603r is a dual issue processor with out -of-order execution capability, care must be taken in how the power management
mode is entered. Furthermore, nap and sleep modes require all outstanding bus operations to be completed before the power man-
agement mode is entered. Normally during system configuration time, one of the power management modes would be selected by
setting the appropriate HID0 mode bit. Later on, the power management mode is invoked by setting the MSR[POW] bit. To provide a
clean transition into and out of the power management mode, the stmsr[POW] should be preceded by a sync instruction and followed
by an isync instruction.
3.6.5. Power dissipation
Table 7.Power dissipation
Vdd/AVdd = 2.5
± 5 % V dc, OVdd = 3.3 ± 5 % V dc, GND = 0 V dc, 0°C ≤ TC ≤ 125°C
CPU clock Frequency
166 MHz
200 MHz
Units
Full-On Mode (DPM Enabled)
Typical
2.1
2.5
W
Max
3.2
4.0
W
Doze Mode
Typical
1.5
1.7
W
Nap Mode
Typical
100
120
mW
Sleep Mode
Typical
96
110
mW
Sleep Mode-PLL Disabled
Typical
60
mW
Sleep Mode-PLL and SYSCLK Disabled
Typical
25
mW
Maximum
60
mW
Notes:
1 Thesevalues apply for all valid PLL_CFG[0–3] settings and do not include output driver power (OVDD) or analog supply power (AVDD). OVDD
power is system dependent but is typically
≤ 10% of VDD. Worst–case AVDD = 15 mW.
2 Typical power is an average value measured at VDD=AVDD=2.5 V, OVV=3.3 V, in a system executing typical applications and benchmark
sequences.
3 Maximum power is measured at VDD=2.625 V using a worst–case instruction mix.
4 To calculate the power consumption at low temperature (–55
°C), use a factor of 1.25.
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