- 您现在的位置：买卖IC网 > PDF目录199494 > TSPC603RMAB/Q6LC 32-BIT, 166 MHz, RISC PROCESSOR, CQFP240 PDF资料下载
参数资料
| 型号： | TSPC603RMAB/Q6LC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 166 MHz, RISC PROCESSOR, CQFP240 |
| 封装： | CERQUAD-240 |
| 文件页数： | 9/40页 |
| 文件大小： | 670K |
| 代理商： | TSPC603RMAB/Q6LC |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页
TSPC603r
in CERQUAD and MQUAD Packages
17/40
4.3. Dynamic characteristics
4.3.1. Clock AC specifications
Table 9 provides the clock AC timing specifications as defined in Figure 4.
Table 9.Clock AC timing specifications
Vdd = AVdd = 2.5 V
± 5 % ; OVdd = 3.3 ± 5 % V dc, GND = 0 V dc, –55°C ≤ TC ≤ 125°C
Num
Characteristics
166 MHz
200 MHz
Unit
Note
Min
Max
Min
Max
Processor frequency
150
166
150
200
MHz
5
VCO frequency
300
332
300
400
MHz
5
SYSCLK (bus) frequency
25
66.7
33.3
66.7
MHz
5
1
SYSCLK cycle time
15
30
13.3
30
ns
2,3
SYSCLK rise and fall time
–
2.0
–
2.0
ns
1
4
SYSCLK duty cycle (1.4V mea-
sured)
40.0
60.0
40.0
60.0
%
3
SYSCLK jitter
–
±150
–
±150
ps
2
603r internal PLL relock time
–
100
–
100
ms
3,4
Notes:
1. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
2. Cycle-to-cycle jitter is guaranteed by design.
3. Timing is guaranteed by design and characterization, and is not tested.
4. PLL relock time is the maximum amount of time required for PLL lock after a stable Vdd, OVdd, AVdd and SYSCLK are reached during the
power-onreset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode.
Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL relock time (100
ms) during the power-on reset
sequence.
5. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core)
frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3]
signal description for valid PLL_CFG[0–3] settings.
Figure 4 : SYSCLK input timing diagram
相关PDF资料 |
PDF描述 |
|---|---|
| TSPC860MHVGB/Q40B | 32-BIT, 40 MHz, MICROPROCESSOR, CBGA357 |
| TSPC860MHMZPB/Q40B | 32-BIT, 40 MHz, MICROPROCESSOR, PBGA357 |
| TS(X)PC860MHMZPU40B | 32-BIT, 40 MHz, MICROPROCESSOR, PBGA357 |
| TS(X)PC860MHMZPU/T50B | 32-BIT, 50 MHz, MICROPROCESSOR, PBGA357 |
| TS(X)PC860MHMZPB/Q50B | 32-BIT, 50 MHz, MICROPROCESSOR, PBGA357 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSPC603RMG10LC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| TSPC603RMG12LC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| TSPC603RMG14LC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| TSPC603RMG6LC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
| TSPC603RMG8LC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC |
发布紧急采购，3分钟左右您将得到回复。