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| 型号： | TSPC603RMAB/Q6LC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 166 MHz, RISC PROCESSOR, CQFP240 |
| 封装： | CERQUAD-240 |
| 文件页数： | 30/40页 |
| 文件大小： | 670K |
| 代理商： | TSPC603RMAB/Q6LC |
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36/40
TSPC603r
in CERQUAD and MQUAD Packages
9. CLOCK RELATIONSHIPS CHOICE
The 603r microprocessors offer customers numerous clocking options. An internal phase-lock loop synchronizes the processor
(CPU) clock to the bus or system clock (SYSCLK) at various ratios.
Inside each PowerPC microprocessor is a phase-lock loop circuit. A voltage controlled oscillator (VCO) is precisely controlled in fre-
quency and phase by a frequency/phase detector which compares the input bus frequency (SYSCLK frequency) to a submultiple of
the VCO.
The ratio of CPU to SYSCLK frequencies is often referred to as the bus mode (for example, 2:1 bus mode).
In the Table 15, the horizontal scale represents the bus frequency (SYSCLK) and the vertical scale represents the PLL–CFG[0–3]
signals.
For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation.
Table 15.CPU frequencies for common bus frequencies and multipliers
PLL_CFG[0–3]
CPU Frequency in MHZ (VCO Frequency in MHz)
Bus–to–
Core
Multiplier
Core–to
VCO
Multiplier
Bus
25 MHz
Bus
33.33
MHz
Bus
40 MHz
Bus
50 MHz
Bus
60 MHz
Bus
66.67 MHz
0100
2x
–
0101
2x
4x
–
0110
2.5x
2x
–
150
(300)
166
(333)
1000
3x
2x
–
150
(300)
180
(360)
200
(400)
1110
3.5x
2x
–
175
(350)
–
1010
4x
2x
–
160
(320)
200
(400)
–
0111
4.5x
2x
–
150
(300)
180
(360)
–
1011
5x
2x
–
166
(333)
200
(400)
–
1001
5.5x
2x
–
183
(366)
–
1101
6x
2x
150
(300)
200
(400)
–
0011
PLL bypass
1111
Clock off
Notes :
1. Some PLL configurations may select bus, CPU or VCO frequencies which are not supported
2. In PLL–bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and
the bus mode is set for 1:1 mode operation. This mode is intended for factory use only.
Note : the AC timing specifications given in this document do not apply in PLL–bypass mode.
3. In clock–off mode, no clocking occurs inside the 603r regardless of the SYSCLK input.
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