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参数资料
| 型号： | TSPC603RMAB/Q6LC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 166 MHz, RISC PROCESSOR, CQFP240 |
| 封装： | CERQUAD-240 |
| 文件页数： | 10/40页 |
| 文件大小： | 670K |
| 代理商： | TSPC603RMAB/Q6LC |
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18/40
TSPC603r
in CERQUAD and MQUAD Packages
4.3.2. Input AC specifications
Table 10 provides the input AC timing specifications for the 603r as defined in Figure 5 and Figure 6.
Table 10.Input AC timing specifications
Vdd = AVdd = 2.5 V
± 5 % ; OVdd = 3.3 ± 5 % V dc, GND = 0 V dc, –55°C ≤ TC ≤ 125°C
Num
Characteristics
166,200 MHz
Unit
Note
Min
Max
10a
Address/data/transfer attribute inputs valid to SYSCLK
(input setup)
2.5
-
ns
2
10b
All other inputs valid to SYSCLK (input setup)
4.0
-
ns
3
10c
Mode select inputs valid to HRESET (input setup) (for
DRTRY, QACK and TLBISYNC)
8
-
tsysclk
4,5,6,7
11a
SYSCLK to address/data/transfer attribute inputs
invalid (input hold)
1.0
-
ns
2
11b
SYSCLK to all other inputs invalid (input hold)
1.0
-
ns
3
11c
HRESET to mode select inputs invalid (input hold) (for
DRTRY, QACK, and TLBISYNC)
0
-
ns
4,6,7
Notes :
1. All input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V of the rising edge of the input
SYSCLK. Both input and output timings are measured at the pin. See Figure 6.
2. Address/data/transfer attribute input signals are composed of the following: A[0–31], AP[0–3], TT[0–4], TC[0–1], TBST, TSIZ[0–2], GBL,
DH[0–31],DL[0–31], DP[9–7].
3. All other input signals are composed of the following: TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA, DBDIS, HRESET,
SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET. See Figure 6.
5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
6. These values are guaranteed by design, and are not tested.
7. This specification is for configuration mode only. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL
relock time (100
ms) during the power-on reset sequence.
Figure 5 : Input timing diagram
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