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参数资料
| 型号： | TSPC603RMAB/Q6LC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 166 MHz, RISC PROCESSOR, CQFP240 |
| 封装： | CERQUAD-240 |
| 文件页数： | 5/40页 |
| 文件大小： | 670K |
| 代理商： | TSPC603RMAB/Q6LC |
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TSPC603r
in CERQUAD and MQUAD Packages
13/40
3.6.1. Dynamic Power Management
Dynamic power management automatically powers up and down the individual execution units of the 603r, based upon the contents
of the instruction stream. For example, if no floating-point instructions are being executed, the floating-point unit is automatically pow-
ered down. Power is not actually removed from the execution unit ; instead, each execution unit has an independent clock input, which
is automatically controlled on a clock-by- clock basis. Since CMOS circuits consume negligible power when they are not switching,
stopping the clock to an execution unit effectively eliminates its power consumption. The operation of DPM is completely transparent
to software or any external hardware. Dynamic power management is enabled by setting bit 11 in HID0 on power-up, of following
HRESET.
3.6.2. Programmable Power Modes
The 603r provides four programmable power states - full power, doze, nap and sleep. Software selects these modes by setting one
(and only one) of the three power saving mode bits. Hardware can enable a power management state through external asynchronous
interrupts The hardware interrupt causes the transfer of program flow to interrupt handler code. The appropriate mode is then set by
the software. The 603r provides a separate interrupt and interrupt vector for power management - the system management interrupt
(SMI). The 603r also contains a decrement timer which allows it to enter the nap or doze mode for a predetermined amount of time and
then return to full power operation through the decrementer interrupt (DI). Note that the 603r cannot switch from on power manage-
ment mode to another without first returning to full on mode. The nap and sleep modes disable bus snooping ; therefore, a hardware
handshake is provided to ensure coherency before the 603r enters these power management modes. AUCUN LIEN summarizes
the four power states.
Table 6.Power PC 603r Microprocessor Programmable Power Modes
PM Mode
Functioning Units
Activation Method
Full-Power Wake Up Method
Full power
All units active
–
Full power (with DPM)
Requested logic by
demand
By instruction dispatch
–
Doze
- Bus snooping
- Data cache as needed
- Decrementer timer
Controlled by SW
External asynchronous exceptions*
Decrementer interrupt
Reset
Nap
Decrementer timer
Controlled by hardware and
software
External asynchronous exceptions
Decrementer interrupt
Reset
Sleep
None
Controlled by hardware and
software
External asynchronous exceptions
Reset
* Exceptions are referred to as interrupts in the architecture specification
3.6.3. Power Management Modes
The following sections describe the characteristics of the 603r’s power management modes, the requirements for entering and exiting
the various modes, and the system capabilities provided by the 603r while the power management modes are active.
1.
Full-Power Mode with DPM Disabled
Full-power mode with DPM disabled power mode is selected when the DPM enable bit (bit 11) in HID0 is cleared.
- Default state following power-up and HRESET.
- All functional units are operating at full processor speed at all times.
2.
Full-Power Mode with DPM Enabled
Full-power mode with DPM enabled (HID0[11] = 1) provides on-chip power management without affecting the functionality or perfor-
mance of the 603r.
- Required functional units are operating at full processor speed.
- Functional units are clocked only when needed.
- No software or hardware intervention required after mode is set.
- Software/hardware and performance transparent.
3.
Doze Mode
Doze ode disables most functional units but maintains cache coherency by enabling the bus interface unit and snooping. A snoop hit
will cause the 603r to enable the data cache, copy the data back to memory, disable the cache, and fully return to the doze state.
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