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参数资料
| 型号： | TSPC603RMAB/Q6LC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 166 MHz, RISC PROCESSOR, CQFP240 |
| 封装： | CERQUAD-240 |
| 文件页数： | 34/40页 |
| 文件大小： | 670K |
| 代理商： | TSPC603RMAB/Q6LC |
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4/40
TSPC603r
in CERQUAD and MQUAD Packages
1. INTRODUCTION
The 603r is a low-power implementation of the PowerPC microprocessor family of reduced instruction set commuter (RISC) micropro-
cessors. The 603r implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer data
types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architec-
ture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture.
The 603r provides four software controllable power-saving modes. Three of the modes (the nap, doze, and sleep modes) are static in
nature, and progressively reduce the amount of power dissipated by the processor. The fourth is a dynamic power management
mode that causes the functional units in the 603r to automatically enter a low-power mode when the functional units are idle without
affecting operational performance, software execution, or any external hardware.
The 603r is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute
out of order for increased performance ; however, the 603r makes completion appear sequential.
The 603 e integrates five execution units - an integer unit (IU), a floating-point unit (FPU), a branch processing unit (BPU), a load/store
unit (LSU) and a system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with
rapid execution times yield high efficiency and throughput for 603r-based systems. Most integer instructions execute in one clock
cycle. The FPU is pipelined so a single-precision multiply-add instruction can be issued every clock cycle.
The 603r provides independent on-chip, 16 Kbyte, four-way set-associative, physically addressed caches for instructions and data
and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data
and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address
translation and variable-sized block translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The
603r also supports block address translation through the use of two independent instruction and data block address translation (IBAT
and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during
block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT
translation takes priority.
The 603r has a selectable 32 - or 64-bit - data bus and a 32-bit address bus. The 603r interface protocol allows multiple masters to
compete for system resources through a central external arbiter. The 603r provides a three-state coherency protocol that supports the
exclusive, modified, and invalid cache states. This protocol as a compatible subset of the MESI (modified/exclusive/shared/invalid)
four-state protocol and operates coherently in systems that contain four-state caches. The 603r supports single-beat and burst data
transfers for memory accesses, and supports memory-mapped I/O.
The 603r uses an advanced, 0.29
mm 5 metal layer CMOS process technology and maintains full interface compatibility with TTL
devices.
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