参数资料
型号: TWR-MPC8309
厂商: Freescale Semiconductor
文件页数: 14/81页
文件大小: 0K
描述: TOWER SYSTEM MODULE MPC8309
设计资源: TWR-MPC8309 Schematic
标准包装: 1
系列: PowerQUICC II™ PRO
类型: MPU
适用于相关产品: Freescale 电源塔系统
所含物品: 板,线缆
DDR2 SDRAM
Table 9. RESET initialization timing specifications (continued)
Input setup time for POR configuration signals
4
t SYS_CLK_IN
1, 2
(CFG_RESET_SOURCE[0:3]) with respect to negation of PORESET
Input hol d time for POR config signals with respect to negation of
0
ns
1, 2
HRESET
Notes:
1. t SYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. For more details, see the MPC 8309 PowerQUICC
II Pro Integrated Communications Processor Family Reference Manual .
2. POR configuration signals consist of CFG_RESET_SOURCE[0:3].
The following table provides the PLL lock times.
Table 10. PLL lock times
PLL lock times
Parameter/Condition
Min
Max
100
Unit
μ s
Note
5.1
Reset signals DC electrical characteristics
The following table provides the DC electrical characteristics for the MPC8309 reset signals mentioned in
Table 11. Reset signals DC electrical characteristics
Characteristic
Output high voltage
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
Symbol
V OH
V OL
V OL
V IH
V IL
I IN
Condition
I OH = –6.0 mA
I OL = 6.0 mA
I OL = 3.2 mA
0 V ≤ V IN ≤ OV DD
Min
2.4
2.0
–0.3
Max
0.5
0.4
OV DD + 0.3
0.8
±5
Unit
V
V
V
V
V
μ A
Note
1
1
1
1
Note:
1. This specification applies when operating from 3.3 V supply.
6
DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface of the
MPC8309. Note that DDR2 SDRAM is GV DD (typ) = 1.8 V.
6.1
DDR2 SDRAM DC electrical characteristics
The following table provides the recommended operating conditions for the DDR2 SDRAM component(s)
of the MPC8309 when GV DD (typ) = 1.8 V .
The following table provides the DDR2 capacitance when GV DD (typ) = 1.8 V.
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
14
Freescale Semiconductor
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