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| 型号： | TWR-MPC8309 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 67/81页 |
| 文件大小： | 0K |
| 描述： | TOWER SYSTEM MODULE MPC8309 |
| 设计资源： | TWR-MPC8309 Schematic |
| 标准包装： | 1 |
| 系列： | PowerQUICC II™ PRO |
| 类型： | MPU |
| 适用于相关产品： | Freescale 电源塔系统 |
| 所含物品： | 板，线缆 |
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Clocking
Configuration chapter in the MPC8309 PowerQUICC II Pro Integrated Communications Processor
Family Reference Manual .
The qe_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF])
and the QUICC Engine PLL division factor (RCWL[CEPDF]) as the following equation:
qe_clk = (QE_CLK_IN × CEPMF) ÷ (1 + CEPDF)
Eqn. 3
For more information, see the QUICC Engine PLL Multiplication Factor section and the “QUICC Engine
PLL Division Factor” section in the MPC8309 PowerQUICC II Pro Integrated Communications
Processor Family Reference Manual for more information.
The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk .
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
( ÷ 2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk .
The local bus memory controller operates with a frequency equal to the frequency of csb_clk . Note that
lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the
external local bus clock outputs (LCLK). The LBC clock divider ratio is controlled by LCRR[CLKDIV].
For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8309 PowerQUICC
II Pro Integrated Communications Processor Family Reference Manual .
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset.
The following table specifies which units have a configurable clock frequency. For detailed description,
refer to the “System Clock Control Register (SCCR)” section in the MPC8309 PowerQUICC II Pro
Integrated Communications Processor Family Reference Manual .
Table 56. Configurable clock units
Unit
I2C,SDHC, USB, DMA Complex
Default Frequency
csb_clk
Options
Off, csb_clk, csb_clk /2, csb_clk /3
NOTE
Setting the clock ratio of these units must be performed prior to any access
to them.
The following table provides the maximum operating frequencies for the MPC8309 MAPBGA under
recommended operating conditions (see Table 2 ).
Table 57. Operating Frequencies for MAPBGA
Characteristic 1
e300 core frequency ( core_clk )
Coherent system bus frequency ( csb_clk )
QUICC Engine frequency ( qe_clk )
Max Operating Frequency
417
167
233
Unit
MHz
MHz
MHz
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
Freescale Semiconductor
67
相关PDF资料 |
PDF描述 |
|---|---|
| TWR-PXN20-KIT | TOWER SYSTEM KIT PXN20 |
| TWR-PXS2010-KIT | TOWER SYSTEM KIT PXS2010 |
| TWR-PXS3020-KIT | TOWER SYSTEM KIT PXS3020 |
| TWR-S08DC-PT60 | TOWER SYSTEM BOARD S08PT60 |
| TWR-S08JE128-KIT | KIT TOWER FOR MC9S08JE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TWR-P1025 | 功能描述:开发板和工具包 - 其他处理器 TOWER MODULE P1025 RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| TWR-P1025-KIT | 功能描述:开发板和工具包 - 其他处理器 QORIQ P1 TWR KIT RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| TWRPI-BLE-DEMO | 功能描述:蓝牙/802.15.1 开发工具 TWRPI-BLE-DEMO RoHS:否 制造商:Panasonic Electronic Components 产品:Bluetooth Evaluation Kit 工具用于评估:PAN1721 频率:2.4 GHz 接口类型:I2C 工作电源电压:2 V to 3.6 V |
| TWRPI-MMA6900 | 功能描述:加速传感器开发工具 MMA6900 SENSOR PLUG-IN RoHS:否 制造商:Murata 工具用于评估:SCA3100-D04 加速:2 g 传感轴:Triple Axis 接口类型:SPI 工作电压:3.3 V |
| TWRPI-MMA845XQ | 功能描述:加速传感器开发工具 Accel TWRPI RoHS:否 制造商:Murata 工具用于评估:SCA3100-D04 加速:2 g 传感轴:Triple Axis 接口类型:SPI 工作电压:3.3 V |
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