参数资料
型号: TWR-MPC8309
厂商: Freescale Semiconductor
文件页数: 16/81页
文件大小: 0K
描述: TOWER SYSTEM MODULE MPC8309
设计资源: TWR-MPC8309 Schematic
标准包装: 1
系列: PowerQUICC II™ PRO
类型: MPU
适用于相关产品: Freescale 电源塔系统
所含物品: 板,线缆
DDR2 SDRAM
Table 15. DDR2 SDRAM input AC timing specifications
At recommended operating conditions with GV DD of 1.8V ± 100mV.
Parameter
Controller skew for MDQS—MDQ/MDM
Symbol
t CISKEW
Min
Max
Unit
ps
Note
1, 2
266 MHz
–750
750
Notes:
1. t CISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t DISKEW . This can be
determined by the equation: t DISKEW = ± (T/4 – abs(t CISKEW )) where T is the clock period and abs(t CISKEW ) is the absolute
value of t CISKEW .
The following figure shows the input timing diagram for the DDR controller.
MCK[n]
MCK[n]
MDQS[n]
t MCK
MDQ[x]
D0
D1
t DISKEW
t DISKEW
Figure 4. DDR input timing diagram
6.2.2
DDR2 SDRAM output AC timing specifications
The following table provides the output AC timing specifications for the DDR2 SDRAM interfaces.
Table 16. DDR2 SDRAM output AC timing specifications
At recommended operating conditions with GV DD of 1.8V ± 100mV.
Parameter
MCK cycle time, (MCK/MCK crossing)
ADDR/CMD output setup with respect to MCK
Symbol 1
t MCK
t DDKHAS
Min
5.988
Max
8
Unit
ns
ns
Note
2
3
333 MHz
266 MHz
2.4
2.5
ADDR/CMD output hold with respect to MCK
333 MHz
266 MHz
t DDKHAX
2.4
2.5
ns
3
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
16
Freescale Semiconductor
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