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参数资料
| 型号： | W25Q128BVFIG |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | PROM |
| 英文描述： | 128M X 1 SPI BUS SERIAL EEPROM, PDSO16 |
| 封装： | 0.300 INCH, GREEN, SOIC-16 |
| 文件页数： | 37/74页 |
| 文件大小： | 855K |
| 代理商： | W25Q128BVFIG |
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W25Q128BV
- 42 -
DO
(IO
1)
7.2.23 Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0) (see Figure 2). The
Sector Erase instruction sequence is shown in Figure 21.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase
instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of
the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Sector Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase
instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB,
BP2, BP1, and BP0) bits (see Status Register Memory Protection table).
/CS
CLK
DI
(IO
0)
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Instruction (20h)
High Impedance
8
9
29
30
31
24-Bit Address
23
22
2
1
0
*
Mode 0
Mode 3
= MSB
*
Figure 21. Sector Erase Instruction Sequence Diagram
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相关代理商/技术参数 |
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| W25Q128BVFIP | 制造商:WINBOND 制造商全称:Winbond 功能描述:3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
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