参数资料
型号: W25Q16BVSSIG
厂商: Winbond Electronics
文件页数: 14/68页
文件大小: 0K
描述: IC SPI FLASH 16MBIT 8SOIC
标准包装: 90
系列: SpiFlash®
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 16M(2M x 8)
速度: 104MHz
接口: SPI 串行
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.209",5.30mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
W25Q16BV
11.1.6 Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register
(S8 and S7). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable (OTP) protection.
SRP1
0
0
0
1
1
SRP0
0
1
1
0
1
/WP
X
0
1
X
X
Status
Register
Software
Protection
Hardware
Protected
Hardware
Unprotected
Power Supply
Lock-Down (1)
One Time
Program (1)
Description
/WP pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
When /WP pin is low the Status Register locked and can not
be written to.
When /WP pin is high the Status register is unlocked and can
be written to after a Write Enable instruction, WEL=1.
Status Register is protected and can not be written to again
until the next power-down, power-up cycle. (2)
Status Register is permanently protected and can not be
written to.
Note:
1. These features are available upon special order. Please refer to Ordering Information.
2. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
11.1.7 Erase Suspend Status (SUS)
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing an
Erase Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase Resume (7Ah) instruction
as well as a power-down, power-up cycle.
11.1.8 Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
operation. When the QE bit is set to a 0 state (factory default), the /WP pin and /HOLD are enabled.
When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD functions are
disabled.
WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during
standard SPI or Dual SPI operation, the QE bit should never be set to a 1.
- 14 -
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