- 您现在的位置：买卖IC网 > PDF目录1971 > W83L951DG (Nuvoton Technology Corporation of America)IC EMBEDDED CNTRLR 128-LQFP PDF资料下载
参数资料
| 型号： | W83L951DG |
| 厂商： | Nuvoton Technology Corporation of America |
| 文件页数： | 107/112页 |
| 文件大小： | 0K |
| 描述： | IC EMBEDDED CNTRLR 128-LQFP |
| 标准包装： | 90 |
| 系列： | W83 |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 24MHz |
| 连通性： | 主机接口，PS/2，SMBus，UART/USART |
| 外围设备： | PWM，WDT |
| 输入/输出数： | 104 |
| 程序存储器容量： | 64KB（64K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 2K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 8x10b; D/A 2x8b |
| 振荡器型： | 外部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 128-LQFP |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页当前第107页第108页第109页第110页第111页第112页
W83L951DG/W83L951FG
- 90 -
6.17.4.1
Read Command
The device will automatically power-up in the read state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value
ensures that no spurious alteration of the memory content occurs during the power transition. The
device will automatically returns to read state after completing an Embedded Program or Embedded
Erase algorithm.
Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
6.17.4.2
Byte Program Command
The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The
program command sequence is initiated by writing two "unlock" write cycles, followed by the program
set-up command. The program address and data are written next, which in turn initiate the embedded
program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens
later and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising
edge of #CE or #WE (whichever happens first) begins programming using the Embedded Program
Algorithm. Upon executing the algorithm, the system is not required to provide further controls or
timings. The device will automatically provide adequate internally generated program pulses and verify
the programmed cell margin.
The automatic programming operation is completed when the data on DQ7 (also used as Data
Polling) is equivalent to the data written to this bit at which time the device returns to the read mode
and addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device
requires that a valid address to the device be supplied by the system at this particular instance of time
for Data Polling operations. Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a
hardware reset occurs during the programming operation, the data at that particular location will be
corrupted.
Programming is allowed in any sequence and across sector boundaries. Beware that a data "0"
cannot be programmed back to a "1". Attempting to program 0 back to 1, the toggle bit will stop
toggling. Only erase operations can convert "0"s to "1"s.
Refer to the Programming Command Flow Chart using typical command strings and bus operations.
6.17.4.3
Chip Erase Command
Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles, followed by writing the
"set-up" command. Two more "unlock" write cycles are asserted, followed by the chip erase
command.
Chip erase does not require the user to program the device prior to erase. Upon executing the
Embedded Erase Algorithm command sequence the device will automatically erase and verify the
entire memory for an all one data pattern. The erase is performed sequentially on each sectors at the
same time (see "Feature"). The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and
terminates when the data on DQ7 is "1" at which time the device returns to read the mode.
Refer to the Erase Command Flow Chart using typical command strings and bus operations.
相关PDF资料 |
PDF描述 |
|---|---|
| X90100M8IZT1 | IC DIGITAL CAPACITOR NV 8-MSOP |
| X9015WS8T1 | IC XDCP SGL 32-TAP 10K 8-SOIC |
| X9110TV14I-2.7 | IC XDCP SGL 1024TAP 100K 14TSSOP |
| X9111TV14I-2.7T1 | IC XDCP SGL 1024TAP 100K 14TSSOP |
| X9116WS8T2 | IC XDCP 16-TAP 10K CMOS 8-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W83L951FG | 制造商:WINBOND 制造商全称:Winbond 功能描述:Mobile Keyboard and Embedded Controller |
| W84032K05M010 | 制造商:Woodhead Molex 功能描述: |
| W8413G38FT | 制造商:Dynatech 功能描述:28v |
| W8-413G38FT | 制造商:Dynatech 功能描述:28v |
| W84601 | 制造商:Performance Tool 功能描述:16 Blade Mini Feeler Gauge 制造商:PERFORMANCE TOOLS 功能描述:MINI FEELER GAUGE |
发布紧急采购，3分钟左右您将得到回复。