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参数资料
| 型号： | W83L951DG |
| 厂商： | Nuvoton Technology Corporation of America |
| 文件页数： | 56/112页 |
| 文件大小： | 0K |
| 描述： | IC EMBEDDED CNTRLR 128-LQFP |
| 标准包装： | 90 |
| 系列： | W83 |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 24MHz |
| 连通性： | 主机接口，PS/2，SMBus，UART/USART |
| 外围设备： | PWM，WDT |
| 输入/输出数： | 104 |
| 程序存储器容量： | 64KB（64K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 2K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 8x10b; D/A 2x8b |
| 振荡器型： | 外部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 128-LQFP |
| 包装： | 托盘 |
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W83L951DG/W83L951FG
- 44 -
6.3.1.2
PS/2 T/R DATA Registers (PS2DATA) (Default Value: 1111_1111)
Transmit:
The byte written to this register, when PS2_T/R = 1 and PS2_EN = 1 and XMIT_BUSY = 0, is
transmitted automatically by the PS/2 channel control logic. On successful start of this transmission,
the PS2 logic will automatic set XMIT_BUSY to high. If PS2_T/R = 0 or PS2_EN = 0 or XMIT_BUSY =
1, then writes to this register are ignored.
On successful completion of this transmission or upon a Transmit Time-out condition the PS2_T/R
and XMIT_BUSY bit is automatically set to low. The PS2_T/R bit must be written to a HIGH before
initiating another transmission to the remote device.
Note:
Even if PS2_T/R = 1 and PS2_EN = 1 and XMIT_BUSY = 0, writing the transmit Register will
hold the current transmission if RDATA_RDY is set. The automatic PS2 logic forces data to
be read from the Receive Register before allowing a transmission.
An interrupt is generated on the high to low transition of XMIT_BUSY.
All bits of this register are write-only for transmit data, because you always read received data.
Receive:
When PS2_EN=1 and PS2_T/R=0, the PS2 Channel is set to automatically receive data on that
channel (both the CLK and DATA lines will float waiting for the peripheral to initiate a reception by
sending a start bit followed by the data bits). After a successful reception data is placed in this register
and the RDATA_RDY bit is set and the CLK line is forced low by the PS2 channel logic. RDATA_RDY
is cleared and the CLK line is released to hi-z following a read of this register. This automatically holds
off further receive transfers until the 8051 has had a chance to get the data.
Note:
The Receive Register is initialized to 0xFF after a Timeout has occurred.
The channel can be enabled to automatically transmit data (PS2_EN=1) by setting PS2_T/R
while RDATA_RDY is set, however a device (not include host) transmission can hold until the
data has been read from the Receive Register.
An interrupt is generated on the low to high transition of RDATA_RDY.
If a receive timeout (REC_TIMEOUT=1) or a transmit timeout (XMIT_TIMEOUT =1) occurs
the channel is busied (CLK held low) for 300us(Input clock=24MHz) or 600us(Input
clock=12MHz) (Hold Time) to guarantee that the peripheral aborts. Writing to the Transmit
Register will be allowed; however the data written will not be transmitted until the Hold Time
expires.
In the foregoing situation, RDATA_RDY won’t automatically clear.
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