参数资料
型号: W9425G6EB-6I
厂商: WINBOND ELECTRONICS CORP
元件分类: DRAM
英文描述: 16M X 16 DDR DRAM, 0.7 ns, PBGA60
封装: 8 X 13 MM, ROHS COMPLIANT, TFBGA-60
文件页数: 19/51页
文件大小: 2017K
代理商: W9425G6EB-6I
W9425G6EB
Publication Release Date:Feb. 12, 2009
- 26 -
Revision A02
9.5 DC Characteristics
MAX.
SYM.
PARAMETER
-5
-6I
UNIT NOTES
IDD0
Operating current: One Bank Active-Precharge;
tRC = tRC min; tCK = tCK min;
DQ, DM and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles
110
7
IDD1
Operating current: One Bank Active-Read-Precharge;
Burst = 4; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA;
Address and control inputs changing once per clock cycle
150
7, 9
IDD2P
Precharge Power Down standby current:
All Banks Idle; Power down mode;
CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM
20
IDD2F
Idle floating standby current:
CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min;
Address and other control inputs changing once per clock cycle;
Vin = VREF for DQ, DQS and DM
45
7
IDD2N
Idle standby current:
CS
> VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min;
Address and other control inputs changing once per clock cycle;
Vin > VIH min or Vin < VIL max for DQ, DQS and DM
45
7
IDD2Q
Idle quiet standby current:
CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min;
Address and other control inputs stable;
Vin > VREF for DQ, DQS and DM
40
7
IDD3P
Active Power Down standby current:
One Bank Active; Power down mode;
CKE < VIL max; tCK = tCK min;
Vin = VREF for DQ, DQS and DM
20
IDD3N
Active standby current:
CS > VIH min; CKE > VIH min; One Bank Active-Precharge;
tRC = tRAS max; tCK = tCK min;
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle
70
7
IDD4R
Operating current:
Burst = 2; Reads; Continuous burst; One Bank Active;
Address and control inputs changing once per clock cycle;
CL=2; tCK = tCK min; IOUT = 0mA
180
170
7, 9
IDD4W
Operating current:
Burst = 2; Write; Continuous burst; One Bank Active;
Address and control inputs changing once per clock cycle;
CL = 2; tCK = tCK min;
DQ, DM and DQS inputs changing twice per clock cycle
180
170
7
IDD5
Auto Refresh current: tRC = tRFC min
190
7
IDD6
Self Refresh current: CKE < 0.2V; external clock on; tCK = tCK min
3
IDD7
Random Read current: 4 Banks Active Read with activate every 20nS,
Auto-Precharge Read every 20 nS;
Burst = 4; tRCD = 3; IOUT = 0mA;
DQ, DM and DQS inputs changing twice per clock cycle;
Address changing once per clock cycle
300
mA
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