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| 型号： | W989D2CBJX6E |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 16M X 32 DDR DRAM, 5.4 ns, PBGA90 |
| 封装： | 8 X 13 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-90 |
| 文件页数： | 5/67页 |
| 文件大小： | 1469K |
| 代理商： | W989D2CBJX6E |
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W989D6CB / W989D2CB
512Mb Mobile LPSDR
Publication Release Date: Jun, 27, 2011
- 13 -
Revision A01-004
Note :
1.
Conditions outside the limits listed under
“ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
Exposure to
“ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect deice reliability.
2.
All voltages are referenced to VSS and VSSQ.
3.
These parameters depend on the cycle rate. These values are measured at a cycle rate with the minimum values of tCK and tRC .
Input signals transition once per tCK period.
4.
These parameters depend on the output loading. Specified values are obtained with the output open.
5.
Power-up sequence is described in Note 9.
6.
AC TEST CONDITIONS : (refer to 6.6.2)
7.
tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output voltage
levels.
8.
These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as
follows: The number of clock cycles = specified value of timing / clock period (count fractions as a whole number)
9.
Power up Sequence : The SDRAM should be powered up by the following sequence of operations.
a.
Power must be applied to VDD before or at the same time as VDDQ while all input signals are held in the
“NOP” state. The
CLK signal will be applied at power up with power.
b.
After power-up a pause of at least 200 uA is required. It is required that DQM and CKE signals must be held
“High” (VDD
levels ) to ensure that the DQ output is in High-impedance state.
c.
All banks must be precharged.
d.
The Mode Register Set command must be issued to initialize the Mode Register.
e.
The Extended Mode Register Set command must be issued to initialize the Extended Mode Register.
f.
Issue two or more Auto Refresh dummy cycles to stabilize the internal circuitry of the device.
The Mode Register Set command can be invoked either before or after the Auto Refresh dummy cycles.
6.6.3 AC Latency Characteristics
CKE to clock disable (CKE Latency)
1
Cycle
DQM to output in High-Z (Read DQM Latency)
2
DQM to input data delay (Write DQM Latency)
0
Write command to input data (Write Data Latency)
0
CS to Command input ( CS Latency)
0
Precharge to DQ Hi-Z Lead time
CL = 2
2
CL = 3
3
Precharge to Last Valid data out
CL = 2
1
CL = 3
2
Burst Stop Command to DQ Hi-Z Lead time
CL = 2
2
CL = 3
3
Burst Stop Command to Last Valid data out
CL = 2
1
CL = 3
2
Read with Auto Precharge Command to Active/Ref Command
CL = 2
BL+ tRP
Cycle + ns
CL = 3
BL+ tRP
Write with Auto Precharge Command to Active/Ref Command
CL = 2
BL+1 + tRP
CL = 3
BL+1 + tRP
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W989D2CBJX6I | 制造商:WINBOND 制造商全称:Winbond 功能描述:512Mb Mobile LPSDR |
| W989D2CBJX7E | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip Mobile LPSDR SDRAM 512M-Bit 16Mx32 1.8V 90-Pin VFBGA |
| W989D2CBJX7G | 制造商:WINBOND 制造商全称:Winbond 功能描述:512Mb Mobile LPSDR |
| W989D2KBJX6E | 制造商:Winbond Electronics Corp 功能描述:IC LPSDR SDRAM 512MBIT 90VFBGA |
| W989D2KBJX6I | 制造商:Winbond Electronics Corp 功能描述:IC LPSDR SDRAM 512MBIT 90VFBGA |
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