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| 型号： | WBLXT975BHCA8 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP160 |
| 封装： | ROHS COMPLIANT, PLASTIC, MS-002DD-1, HQFP-160 |
| 文件页数： | 17/76页 |
| 文件大小： | 1004K |
| 代理商： | WBLXT975BHCA8 |
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
24
Datasheet
Collision
The LXT974/975 asserts its collision signal, asynchronously to any clock, whenever the line state
is half-duplex and the transmitter and receiver are active at the same time. Table 14 summarizes the
conditions for assertion of carrier sense, collision, and data loopback signals.
2.2.2.2
MII Management Interface
The LXT974/975 supports the IEEE 802.3 MII Management Interface also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to
monitor and control the state of the LXT974/975. The MDIO interface consists of a physical
connection, a specific protocol that runs across the connection, and an internal set of addressable
registers. Some registers are required and their functions are defined by the IEEE 802.3
specification. Additional registers are allowed for expanded functionality. The LXT974/975 is
configured with both sets of registers.
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this
interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO operates as a
read-only interface. When MDDIS is Low, both read and write are enabled. The timing for the
(read and write). The protocol allows one controller to communicate with up to eight LXT974/975
chips. Bits A4:2 of the 5-bit PHY address are assigned as the LXT974/975 address. Bits A1:0 are
assigned as port addresses 0 through 3. The LXT974/975 supports 12 internal registers per port (48
total), each of which is 16 bits wide.
Figure 7. Loopback Paths
Digital
Block
MII
Analog
Block
FX
Driver
TX
Driver
100TX
Loopback
100FX
Loopback
10T
Loopback
Table 14. Carrier Sense, Loopback, and Collision Conditions
Speed & Duplex Condition
Carrier Sense
Loopback
Collision
Full-Duplex at 10 Mbps or 100 Mbps
Receive Only
None
100 Mbps, Half-Duplex
Transmit or Receive
None
Transmit and Receive
10 Mbps, Half-Duplex, 19.11 = 0
Transmit or Receive
Yes
Transmit and Receive
10 Mbps, Half-Duplex, 19.11 = 1
Transmit or Receive
None
Transmit and Receive
相关PDF资料 |
PDF描述 |
|---|---|
| WBLXT974BHCA8 | DATACOM, ETHERNET TRANSCEIVER, PQFP160 |
| WBLXT974BHCA8 | DATACOM, ETHERNET TRANSCEIVER, PQFP160 |
| WBLXT9785EHC.C2V | DATACOM, INTERFACE CIRCUIT, PQFP208 |
| WBLXT9785EHC.D0-865110 | DATACOM, INTERFACE CIRCUIT, PQFP208 |
| WBLXT9785EHC.D0-865111 | DATACOM, INTERFACE CIRCUIT, PQFP208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| WBLXT9785EHC.D0865110 | 功能描述:IC TXRX 8PORT ETHERNET 208-HQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| WBLXT9785EHC.D0-865110 | 制造商:Cortina Systems Inc 功能描述:PHY 8-CH 10Mbps/100Mbps 208-Pin PQFP |
| WBLXT9785EHC.D0-865111 | 制造商:Cortina Systems Inc 功能描述:PHY 8-CH 10Mbps/100Mbps 208-Pin PQFP |
| WBLXT9785HC.D0 | 功能描述:IC TXRX 8PORT ETHERNET 208-HQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| WBLXT9785HC.D0-865112 | 功能描述:TXRX ETH OCT LP COMM 208-HQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:收发器 驱动器/接收器数:1/1 规程:RS422，RS485 电源电压:4.75 V ~ 5.25 V 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-PDIP 包装:管件 产品目录页面:1402 (CN2011-ZH PDF) |
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