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| 型号： | WBLXT975BHCA8 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP160 |
| 封装： | ROHS COMPLIANT, PLASTIC, MS-002DD-1, HQFP-160 |
| 文件页数： | 37/76页 |
| 文件大小： | 1004K |
| 代理商： | WBLXT975BHCA8 |
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
42
Datasheet
3.1.5
The RBIAS Pin
The LXT974/975 requires a 22 k
Ω, 1% resistor directly connected between the RBIAS pin and
ground. Place the RBIAS resistor as close to the RBIAS pin as possible. Run an etch directly from
the pin to the resistor, and sink the other side of the resistor to a filtered ground. Surround the
RBIAS trace with a filtered ground; do not run high-speed signals next to RBIAS.
3.1.6
The Twisted-Pair Interface
Because the LXT974/975 transmitter uses 2:1 magnetics, system designers must take extra
precautions to minimize parasitic shunt capacitance in order to meet return loss specifications.
These steps include:
Use compensating inductor in the output stage (see Figure 23 on page 47).
Place the magnetics as close as possible to the LXT974/975.
Keep transmit pair traces short.
Route the transmit pair adjacent to a ground plane. The optimum arrangement is to place the
transmit traces two to three layers from the ground plane, with no intervening signals.
Some magnetic vendors are producing magnetics with improved return loss performance. Use
of these improved magnetics increases the return loss budget available to the system designer.
Improve EMI performance by filtering the output center tap. A single ferrite bead may be used
to supply center tap current to all 4 ports. All four ports draw a combined total of
≥270 mA so
the bead should be rated at
≥400 mA.
In addition, follow all the standard guidelines for a twisted-pair interface:
Route the signal pairs differentially, close together. Allow nothing to come between them.
Keep distances as short as possible; both traces should have the same length.
Avoid vias and layer changes as much as possible.
Keep the transmit and receive pairs apart to avoid cross-talk.
Put all the components for the transmit network on the front side of the board (same side as the
LXT974/975).
Put entire receive termination network on the back side of the board.
Bypass common-mode noise to ground on the in-board side of the magnetics using 0.01
μF
capacitors.
Keep termination circuits close together and on the same side of the board.
Always put termination circuits close to the source end of any circuit.
3.1.7
The Fiber Interface
The fiber interface consists of a PECL transmit and receive pair to an external fiber-optic
transceiver. The transmit pair should be AC-coupled to the transceiver, and biased to 3.7V with a
50
Ω equivalent impedance. The receive pair can be DC-coupled, and should be biased to 3.0V
with a 50
Ω equivalent impedance. Figure 24 on page 48 shows the correct bias networks to achieve
these requirements.
相关PDF资料 |
PDF描述 |
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| WBLXT974BHCA8 | DATACOM, ETHERNET TRANSCEIVER, PQFP160 |
| WBLXT974BHCA8 | DATACOM, ETHERNET TRANSCEIVER, PQFP160 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| WBLXT9785EHC.D0865110 | 功能描述:IC TXRX 8PORT ETHERNET 208-HQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| WBLXT9785EHC.D0-865110 | 制造商:Cortina Systems Inc 功能描述:PHY 8-CH 10Mbps/100Mbps 208-Pin PQFP |
| WBLXT9785EHC.D0-865111 | 制造商:Cortina Systems Inc 功能描述:PHY 8-CH 10Mbps/100Mbps 208-Pin PQFP |
| WBLXT9785HC.D0 | 功能描述:IC TXRX 8PORT ETHERNET 208-HQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| WBLXT9785HC.D0-865112 | 功能描述:TXRX ETH OCT LP COMM 208-HQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:收发器 驱动器/接收器数:1/1 规程:RS422，RS485 电源电压:4.75 V ~ 5.25 V 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-PDIP 包装:管件 产品目录页面:1402 (CN2011-ZH PDF) |
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