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| 型号： | WBLXT975BHCA8 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP160 |
| 封装： | ROHS COMPLIANT, PLASTIC, MS-002DD-1, HQFP-160 |
| 文件页数： | 68/76页 |
| 文件大小： | 1004K |
| 代理商： | WBLXT975BHCA8 |
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LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
70
Datasheet
Table 53. Interrupt Status Register (Address 18, Hex 12)
Bit
Name
Description
Type 1
Default
18.15
MINT
1 = Indicates MII interrupt pending.
0 = Indicates no MII interrupt pending. This bit is cleared by reading
Register 1 followed by reading Register 18.
RO
N/A
18.14:0
Reserved
Ignore
RO
0
1. RO = Read Only
Table 54. Port Configuration Register (Address 19, Hex 13)
Bit
Name
Description
Type
1
Default
19.15
Reserved
Write as 0; ignore on read.
R/W
N/A
19.14
Txmit Test
Enable
(100BASETX)
1 = 100BASE-T transmit test enabled (Port transmits data regardless of
receive status).
0 = Normal operation.
R/W
0
19.13
Reserved
Write as 0; ignore on read.
R/W
N/A
19.12
MDIO_INT
1 = Enable interrupt signaling on MDIO (if 17.1 = 1).
0 = Normal operation (MDIO Interrupt disabled).
Bit is ignored unless the interrupt function is enabled
(17.1 = 1).
R/W
0
19.11
TP Loopback
Enable
(10BASE-T)
1 = Disable 10BT Loopback - Data transmitted by the MAC will not
loopback to the RXD and RX_DV pins. Only CRS is looped back.
0 = Enable 10BT Loopback - Preamble, SFD, and data are directly looped
back to the MII.
R/W
0
19.10
SQE Disable
(10BASE-T)
1 = Normal operation (SQE enabled).
0 = Disable SQE.
R/W
0
19.9
Jabber Disable
(10BASE-T)
1 = Disable jabber.
0 = Normal operation (jabber enabled).
R/W
0
19.8
Link Test
Enable
(10BASE-T)
1 = Disable 10BASE-T link integrity test.
0 = Normal operation (10BASE-T link integrity test enabled).
R/W
Note 2
19.7:6
Reserved
Write as 0; ignore on read.
R/W
N/A
19.5
Advance TX
Clock
1 = TX clock is advanced relative to TXD<3:0> and TX_ER by 1/2
TX_CLK cycle.
0 = Normal operation.
R/W
0
19.4
Reserved
Write as 0; ignore on read.
R/W
N/A
1. R/W = Read/Write
2. If auto-negotiation is disabled, the default value of bit 19.8 is determined by pin 115 (CFG_1). If CFG_1 is High, the default
value of
bit 19.8 = 1.
If CFG_1 is Low, the default value of bit 19.8 = 0. If auto-negotiation is enabled, the default value of bit 19.8 = 0.
3. The default value of bit 19.3 is determined by BYPSCR. If BYPSCR is High, the default value of bit 19.3 = 1.
If BYPSCR is Low, the default value of bit 19.3 = 0.
4. The default value of bit 19.2 is determined by the SD/TPn pin for the respective port.
If SD/TPn is tied Low, the default value of bit 19.2 = 0. If SD/TPn is not tied Low, the default value of bit 19.2 = 1.
On the LXT975, this bit is ignored on ports 0 and 2 that operate in twisted-pair mode only.
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相关代理商/技术参数 |
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| WBLXT9785EHC.D0865110 | 功能描述:IC TXRX 8PORT ETHERNET 208-HQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| WBLXT9785EHC.D0-865110 | 制造商:Cortina Systems Inc 功能描述:PHY 8-CH 10Mbps/100Mbps 208-Pin PQFP |
| WBLXT9785EHC.D0-865111 | 制造商:Cortina Systems Inc 功能描述:PHY 8-CH 10Mbps/100Mbps 208-Pin PQFP |
| WBLXT9785HC.D0 | 功能描述:IC TXRX 8PORT ETHERNET 208-HQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
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