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| 型号： | WBLXT975BHCA8 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP160 |
| 封装： | ROHS COMPLIANT, PLASTIC, MS-002DD-1, HQFP-160 |
| 文件页数： | 20/76页 |
| 文件大小： | 1004K |
| 代理商： | WBLXT975BHCA8 |
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Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Datasheet
27
2.3
Initialization
At power-up or reset, the LXT974/975 performs the initialization as shown in Figure 11. Control
mode selection is provided via the MDDIS pin as shown in Table 18. When MDDIS (pin 100) is
High, the LXT974/975 operates in Manual Control Mode. When MDDIS is Low, the LXT974/975
operates in MDIO Control Mode.
2.3.1
MDIO Control Mode
In the MDIO Control Mode, the LXT974/975 uses the Hardware Control Interface to set up initial
(default) values of the MDIO registers. The MDIO Register set for the LXT974/975 is described in
where X is the register number (0-6 or 16-20) and Y is the bit number (0-15). Once initial values
are set, bit control reverts to the MDIO interface.
2.3.2
Manual Control Mode
In the Manual Control Mode, LXT974/975 disables direct write operations to the MDIO registers
via the MDIO interface. The Hardware Control Interface is continuously monitored and the MDIO
registers are updated accordingly.
Table 17. Configuring the LXT974/975 with Auto-Negotiation Disabled
Desired Configuration1,2
Pin Settings
MDIO Registers
SD/TPn
per port
CFG_2
global
CFG_0
global
FDE
global
FDE_FX
0.8
0.13
19.2
Per Port (Fiber) Configuration
Fiber operation can be forced per port via SD/TPn pins when auto-negotiation is enabled. Per-port settings override the global
pin settings.
100FX Full-Duplex
Operation.
High or
PECL3
Ignored
High
1
100FX Half-Duplex
Operation.
High or
PECL3
Ignored
Low
0
1
Global (Twisted-Pair) Configuration5
Force 100TX Full-Duplex
Operation on all ports.4
Low
High
Ignored
1
0
Force 100TX Half-Duplex
Operation on all ports.4
Low
High
Low
Ignored
0
1
0
Force 10T Full-Duplex
Operation on all ports.
Low
High
Ignored
1
0
Force 10T Half-Duplex
Operation on all ports.
Low
Ignored
0
1. Refer to Table 15 for basic configurations.
2. Refer to Table 16 for Hardware Control Interface functions advertised when auto-negotiation is enabled.
3. When SD/TPn is set High or to PECL levels, auto-negotiation is disabled and FDE_FX determines the duplex mode of the
port.
4. CFG_2, CFG_0, and SD/TPn must all be set for 100TX operation.
5. Fiber configuration must be selected on a per-port basis.
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| WBLXT9785EHC.D0865110 | 功能描述:IC TXRX 8PORT ETHERNET 208-HQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,000 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.295"，7.50mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
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