
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
212
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Table 95. Interrupt Status Register (Address 19, Hex 13)
Bit
Name
Description
Type 1
Default2
15:9
Reserved
Write as 0, ignore on Read
R
0
8
RxERCntFUL
RxER Counter Full Status.
0 = The internal counters have not reached maximum
values
1 = One of the internal counters has reached its maximum
value
R/LH
0
7
ANDONE
Auto-Negotiation Status.
0 = Auto-negotiation has not completed
1 = Auto-negotiation has completed
R/LH
N/A
6
SPEEDCHG
Speed Change Status.
0 = A speed change has not occurred since last reading
this register
1 = A speed change has occurred since last reading this
register
R/LH
0
5
DUPLEXCHG
Duplex Change Status.
0 = A duplex change has not occurred since last reading this
register
1 = A duplex change has occurred since last reading this
register
R/LH
0
4LINKCHG
Link Status Change Status.
0 = A link change has not occurred since last reading this
register
1 = A link change has occurred since last reading this
register
R/LH
0
3Isolate
MII Isolate Change Status.
0 = An Isolate change has not occurred since last reading
this register
1 = An Isolate change has occurred since last reading this
register
R/LH
0
2MDINT
0 = Interrupt not pending
1 = Interrupt pending
R/LH
0
1:0
Reserved
R
0
1. R = Read Only, LH = Latching High – cleared when read
2. The default values are updated on completion of reset and reflect the status or change in status at that
time. Intel recommends that the register status be read on completion of reset.