
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Datasheet
141
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
4.8.2
Transmit Enable
TxENn must be asserted and de-asserted synchronously with REFCLK. The MAC must assert
TxENn at the same time as the first nibble of preamble. TxENn must be de-asserted after the last
bit of the packet.
4.8.3
Carrier Sense & Data Valid
The LXT9785/LXT9785E asserts CRS_DVn when it detects activity on the line. However,
RxDatan outputs zeros until the received data is decoded and available for transfer to the controller.
4.8.4
Receive Error
Whenever the LXT9785/LXT9785E receives an error symbol from the network, it asserts RxERn.
When it detects a bad Start-of-Stream Delimiter (SSD) it drives a “10” jam pattern on the RxData
pins to indicate a false carrier event.
4.8.5
Out-of-Band Signaling
The LXT9785/LXT9785E has the capability of encoding status information in the RxData stream
4.8.6
4B/5B Coding Operations
The 100BASE-X protocol specifies the use of a 5-bit symbol code on the network media. However,
data is normally transmitted across the RMII interface in 2-bit nibblets or “di-bits”. The LXT9785/
LXT9785E incorporates a parallel/serial converter that translates between di-bit pairs and 4-bit
nibbles, and a 4B/5B encoder/decoder circuit that translates between 4-bit nibbles and 5-bit
symbols for the 100BASE-X connection.
Figure 24 shows the data conversion flow from nibbles to
Figure 24. RMII Data Flow
D2
D3
D0
D1
Parallel
to
Serial
to
Parallel
D0
D1
D2
D3
4B/5B
S0
S1
S2
S3
S4
MLT3
0
+1
-1
00
Transition = 1.
No Transition = 0.
All transitions must follow
pattern: 0, +1, 0, -1, 0, +1...
Scramble
De-
Scramble
Reduced MII Mode Data Flow
di-bit
pairs
4-bit
nibbles
5-bit
symbols