
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Datasheet
90
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
L4,
M2,
M3,
N1,
N2
88
89
90
91
92
ADD_4
ADD_3
ADD_2
ADD_1
ADD_0
I, ST, ID
Address <4:0>.
Sets base address. Each port adds its port number
(starting with 0) to this address to determine its PHY
address.
Port 0 Address = Base
Port 1 Address = Base + 1
Port 2 Address = Base + 2
Port 3 Address = Base + 3
Port 4 Address = Base + 4
Port 5 Address = Base + 5
Port 6 Address = Base + 6
Port 7 Address = Base + 7
L17,
L16
178
177
MODESEL_1
MODESEL_0
I, ST, ID
Mode Select[1:0].
00 = RMII
01 = SMII
10 = SS-SMII
11 = Reserved
All ports are configured the same. Interfaces cannot be
mixed and must be all RMII, SMII, or SS-SMII.
L15
176
SECTION
I, ST, ID
Sectionalization Select.
This pin selects sectionalization into separate ports.
0 = 1x8 ports,
1 = 2x4 ports
K1
83
AMDIX_EN
I, ST, IP
Auto MDI/MDIX Enable Default.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 27.9 for
all ports. These register bits can be read and
overwritten after startup / reset. Refer to
Table 40When active (High), automatic MDI crossover (MDIX)
(regardless of segmentation) is selected for all ports.
When inactive (Low) MDIX is selected according to the
MDIX pin.
Table 32. Miscellaneous Signal Descriptions – BGA23 (Sheet 2 of 4)
Ball/Pin
Designation
Symbol
Type1
Signal Description2
BGA23
PQFP
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
2. The IP/ID resistors are disabled during hardware power-down mode.
3. The LINKHOLD ability is available only for stepping 4 (Revision D0).