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参数资料
| 型号： | WEDPND16M72S-266BC |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| 封装： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件页数： | 11/16页 |
| 文件大小： | 441K |
| 代理商： | WEDPND16M72S-266BC |
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White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPND16M72S-XBX
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA0 and BA1 select the bank, A0-12 select
the row). The address bits registered coincident with the
READ or WRITE command are used to select the starting
column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information cover-
ing device initialization, register definition, command de-
scriptions and device operation.
DDR SDRAMs must be powered up and initialized in a pre-
defined manner. Operational procedures other than those
specified may result in undefined operation. Power must
first be applied to VCC and VCCQ simultaneously, and then to
VREF (and to the system VTT). VTT must be applied after VCCQ
to avoid device latch-up, which may cause permanent dam-
age to the device. VREF can be applied any time after VCCQ
but is expected to be nominally coincident with VTT. Except
for CKE, inputs are not recognized as valid until after VREF is
applied. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after VCC is applied. Maintaining an LVCMOS LOW
level on CKE during power-up is required to ensure that the
DQ and DQS outputs will be in the High-Z state, where they
will remain until driven in normal operation (by a read ac-
cess). After all power supply and reference voltages are
stable, and the clock is stable, the DDR SDRAM requires a
200
ms delay prior to applying an executable command.
Once the 200
ms delay has been satisfied, a DESELECT or
NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a PRECHARGE
ALL command should be applied. Next a LOAD MODE REG-
ISTER command should be issued for the extended mode
register (BA1 LOW and BA0 HIGH) to enable the DLL, fol-
lowed by another LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL and to
program the operating parameters. Two-hundred clock
cycles are required between the DLL reset and any READ
command. A PRECHARGE ALL command should then be
applied, placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be
performed (tRFC must be satisfied.) Additionally, a LOAD
MODE REGISTER command for the mode register with the
reset DLL bit deactivated (i.e., to program operating param-
eters without resetting the DLL) is required. Following these
requirements, the DDR SDRAM is ready for normal operation.
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
INITIALIZATION
REGISTER DEFINITION
MODE REGISTER
strobe transmitted by the DDR SDRAM during READs and by
the memory contoller during WRITEs. DQS is edge-aligned
with data for READs and center-aligned with data for WRITEs.
Each chip has two data strobes, one for the lower byte and
one for the upper byte.
The 128MB DDR SDRAM operates from a differential clock (CLK and
CLK); the crossing of CLK going HIGH and CLK going LOW will be
referred to as the positive edge of CLK. Commands (address and
control signals) are registered at every positive edge of CLK. Input
data is registered on both edges of DQS, and output data is refer-
enced to both edges of DQS, as well as to both edges of CLK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed. The address bits registered coincident with
the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE
burst lengths of 2, 4, or 8 locations. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
The pipelined, multibank architecture of DDR SDRAMs allows
for concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a power-
saving power-down mode.
FUNCTIONAL DESCRIPTION
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