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| 型号： | WJLXT971ALE.A4-857346 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-64 |
| 文件页数： | 27/80页 |
| 文件大小： | 931K |
| 代理商： | WJLXT971ALE.A4-857346 |
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Page 33
Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver
LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
5.6 MII Operation
5.6.4
Carrier Sense
Carrier Sense (CRS) is an asynchronous output.
CRS is always generated when the LXT972A PHY receives a packet from the line.
CRS is also generated when the LXT972A PHY is in half-duplex mode when a packet
is transmitted.
Table 14 summarizes the conditions for assertion of carrier sense, data loopback, and
collision signals. Carrier sense is not generated when a packet is transmitted and in full-
duplex mode.
.
5.6.5
Error Signals
When the LXT972A PHY is in 100 Mbps mode and receives an invalid symbol from the
network, it asserts RX_ER and drives “0101” on the RXD pins.
When the MAC asserts TX_ER, the LXT972A PHY drives “H” symbols out on the TPFOP/
N pins.
5.6.6
Collision
The LXT972A PHY asserts its collision signal asynchronously to any clock whenever the
line state is half-duplex and the transmitter and receiver are active at the same time.
Table 14 summarizes the conditions for assertion of carrier sense, data loopback, and
collision signals.
5.6.7
Loopback
The LXT972A PHY provides the following loopback functions:
Figure 10 shows LXT972A PHY operational and test loopback paths. (An internal digital
loopback path is not shown.) For more information on loopback functions, see Table 14,
Table 14
Carrier Sense, Loopback, and Collision Conditions
Speed
Duplex Condition
Carrier Sense
Test
Loop-
back1, 2
Operational
Loop-
back1, 2
Collision
100 Mbps
Full-Duplex
Receive Only
Yes
No
None
Half-Duplex
Transmit or Receive
No
Transmit and Receive
10 Mbps
Full-Duplex
Receive Only
Yes
No
None
Half-Duplex,
register bit 16.8 = 0
Transmit or Receive
Yes
Transmit and Receive
Half-Duplex,
register bit 16.8 = 1
Transmit or Receive
No
Transmit and Receive
1. Test Loopback is enabled when register bit 0.14 = 1.
2. For descriptions of Test Loopback and Operational Loopback, see Section 5.6.7, Loopback, on page 33.
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