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| 型号： | WJLXT971ALE.A4-857346 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-64 |
| 文件页数： | 37/80页 |
| 文件大小： | 931K |
| 代理商： | WJLXT971ALE.A4-857346 |
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Page 42
Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver
LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
5.8 10 Mbps Operation
5.7.3.3.4
Programmable Slew Rate Control
The LXT972A PHY device supports a programmable slew-rate mechanism whereby one
of four pre-selected slew rates can be used. (For details, see Table 55, Transmit Control
Register - Address 30, Hex 1E, on page 78.) The slew-rate mechanism allows the
designer to optimize the output waveform to match the characteristics of the magnetics.
Note:
For hardware control of the slew rate, use the TxSLEW pins.
5.8
10 Mbps Operation
The LXT972A PHY operates as a standard 10BASE-T PHY and LXT972A PHY supports
standard 10 Mbps functions. During 10BASE-T operation, the LXT972A PHY transmits
and receives Xilinks* Manchester-encoded data across the network link. When the MAC
is not actively transmitting data, the LXT972A PHY drives link pulses onto the line.
In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-
encoded signals received from the network are decoded by the LXT972A PHY and sent
across the MII to the MAC.
5.8.1
10BASE-T Preamble Handling
The LXT972A PHY offers two options for preamble handling, selected by register bit 16.5.
In 10BASE-T mode when register bit 16.5 = 0, the LXT972A PHY strips the entire
preamble off of received packets. CRS is asserted coincident with the start of the
preamble. RX_DV is held Low for the duration of the preamble. When RX_DV is
asserted, the very first two nibbles driven by the LXT972A PHY are the SFD “5D” hex
followed by the body of the packet.
In 10BASE-T mode when register bit 16.5 = 1, the LXT972A PHY passes the
preamble through the MII and asserts RX_DV and CRS simultaneously. (In
10BASE-T loopback, the LXT972A PHY loops back whatever the MAC transmits to it,
including the preamble.)
5.8.2
10BASE-T Carrier Sense
For 10BASE-T links, CRS assertion is based on reception of valid preamble, and CRS de-
assertion is based on reception of an end-of-frame (EOF) marker. register bit 16.7 allows
CRS de-assertion to be synchronized with RX_DV de-assertion. For details, see Table 49,
5.8.3
10BASE-T Dribble Bits
The LXT972A PHY handles dribble bits in all modes. If one to four dribble bits are
received, the nibble is passed across the MII, padded with ones if necessary. If five to
seven dribble bits are received, the second nibble is not sent to the MII bus.
5.8.4
10BASE-T Link Integrity Test
In 10BASE-T mode, the LXT972A PHY always transmits link pulses.
If the Link Integrity Test function is enabled (the normal configuration), the LXT972A
PHY monitors the connection for link pulses. Once link pulses are detected, data
transmission is enabled and remains enabled as long as either the link pulses or data
transmission continue. If the link pulses stop, the data transmission is disabled.
相关PDF资料 |
PDF描述 |
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| WJLXT972ALC.A4-857341 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT972ALC.A4-857345 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
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