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| 型号： | WJLXT971ALE.A4-857346 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-64 |
| 文件页数： | 70/80页 |
| 文件大小： | 931K |
| 代理商： | WJLXT971ALE.A4-857346 |
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Page 72
Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver
LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
9.0 Register Definitions -
Product-Specific Registers
16.8
TP Loopback
(10BASE-T)
0 = Normal operation
1 = Disable TP loopback during half-duplex
operation
R/W
0
16.7
CRS Select
(10BASE-T)
0 = Normal Operation
1 = CRS deassert extends to RX_DV deassert
R/W
1
16.6
Reserved
Write as ‘0’. Ignore on Read.
R/W
0
16.5
PRE_EN
Preamble Enable.
0 = Set RX_DV high coincident with SFD.
1 = Set RX_DV high and RXD = preamble when
CRS is asserted.
Note:
Preamble is always enabled in 100 Mbps
operation.
R/W
0
16.4:3
Reserved
Write as ‘0’. Ignore on Read.
R/W
00
16.2
Reserved
Write as ‘0’. Ignore on Read.
R/W
0
16.1
Alternate NP feature
0 = Disable alternate auto negotiate next page
feature.
1 = Enable alternate auto negotiate next page
feature.
Note:
This bit enables or disables the register
bit 6.5 capability.
R/W
0
16.0
Reserved
Write as ‘0’. Ignore on Read.
R/W
0
Table 50
Status Register #2 - Address 17, Hex 11 (Sheet 1 of 2)
Bit
Name
Description
Type 1
Default
17.15
Reserved
Always 0.
RO
0
17.14
10/100 Mode
0 = LXT972A PHY is not operating 100BASE-TX
mode.
1 = LXT972A PHY is operating in 100BASE-TX
mode.
RO
0
17.13
Transmit Status
0 = LXT972A PHY is not transmitting a packet.
1 = LXT972A PHY is transmitting a packet.
RO
0
17.12
Receive Status
0 = LXT972A PHY is not receiving a packet.
1 = LXT972A PHY is receiving a packet.
RO
0
17.11
Collision Status
0 = No collision.
1 = Collision is occurring.
RO
0
17.10
Link
0 = Link is down.
1 = Link is up.
RO
0
17.9
Duplex Mode
0 = Half-duplex.
1 = Full-duplex.
RO
0
17.8
Auto-Negotiation
0 = LXT972A PHY is in manual mode.
1 = LXT972A PHY is in auto-negotiation mode.
RO
0
1. RO = Read Only. R/W = Read/Write
Table 49
Configuration Register - Address 16, Hex 10 (Sheet 2 of 2)
Bit
Name
Description
Type 1
Default
1. R/W = Read /Write
相关PDF资料 |
PDF描述 |
|---|---|
| WJLXT972ALC.A4-857341 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT972ALC.A4-857345 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT971ALC.A4SE000 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| WJLXT971ALC.A4SE001 | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
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| WJLXT971CA4 | 制造商:Intel 功能描述: |
| WJLXT972ALC.A4 | 功能描述:IC TRANS 3.3V ETHERNET 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件 |
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| WJLXT972ALC.A4-857341 | 功能描述:TXRX ETH 10/100 SGL PORT 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:收发器 驱动器/接收器数:1/1 规程:RS422，RS485 电源电压:4.75 V ~ 5.25 V 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-PDIP 包装:管件 产品目录页面:1402 (CN2011-ZH PDF) |
| WJLXT972ALC.A4-857345 | 功能描述:TXRX ETH 10/100 SGL PORT 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1 系列:- 类型:线路收发器 驱动器/接收器数:5/3 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:Digi-Reel® 产品目录页面:918 (CN2011-ZH PDF) 其它名称:296-25096-6 |
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