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| 型号： | WLA49VVA |
| 厂商： | National Semiconductor Corporation |
| 元件分类： | ADC |
| 英文描述： | Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC |
| 中文描述： | 音频子系统的双模单声道立体声耳机和扬声器放大器的高效率和多功能模数转换器 |
| 文件页数： | 20/112页 |
| 文件大小： | 5017K |
| 代理商： | WLA49VVA |
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10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_V
DD = 3.3V, D_VDD = 3.3V,
BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless
otherwise stated. Limits apply for 25C. (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits.
Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device
is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device
performance.
Note 2: All voltages are measured with respect to the relevant VSS pin unless otherwise specified. All grounds should be coupled as close as possible to the device.
Note 3: The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX =(TJMAX –TA)/ θJA or the number given in Absolute Maximum Ratings, whichever is lower.
Note 4: Human body model: 100pF discharged through a 1.5k
resistor.
Note 5: Machine model: 220pF – 240pF discharged through all pins.
Note 6: Typical values are measured at 25C and represent the parametric norm.
Note 7: Limits are guaranteed to Nationals AOQL (Average Outgoing Quality Level).
Note 8: Best operation is achieved by maintaining 3.0V < A_VDD < 5.0 and 3.0V < D_VDD < 3.6V and A_VDD > D_VDD.
Note 9: Digital shutdown current is measured with system clock set for PLL output while the PLL is disabled.
Note 10: Disabling or bypassing the PLL will usually result in an improvement in noise measurements.
LM4935
www.national.com
15
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