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参数资料
| 型号： | WLA49VVA |
| 厂商： | National Semiconductor Corporation |
| 元件分类： | ADC |
| 英文描述： | Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC |
| 中文描述： | 音频子系统的双模单声道立体声耳机和扬声器放大器的高效率和多功能模数转换器 |
| 文件页数： | 37/112页 |
| 文件大小： | 5017K |
| 代理商： | WLA49VVA |
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12.0 Status & Control Registers (Continued)
These tables cover the most common applications, obtaining clocks for derivative sample rates such as 22.05 kHz should be
done by increasing the P divider value or using the R/Q dividers.
If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining
12.000 MHz from 1.536 MHz is shown below (this is typical for deriving DAC clocks from I2S datastreams).
Choose a small range of P so that the VCO frequency is swept between 40 MHz and 60 MHz. So for P = 3 to 5, sweep the M
inputs from 1 to 3. The most accurate N and N_MOD can be calculated by:
N = FLOOR(((Fout/Fin)*(P*M)),1)
N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0)
This shows that settingM=1,N= 39+1/16, P = 5 (i.e. PLL_M = 0, PLL_N = 39, PLL_N_MOD = 2, & PLL_P = 4) gives a
comparison frequency of 1.5 MHz, a VCO frequency of 60 MHz and an output frequency of 12.000 MHz. The same settings can
be used to get 11.025 from 1.4112 MHz for 44.1 kHz sample rates.
Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used but an exact
frequency match cannot be found. The I2S should be master on the LM4935 so that the data source can support appropriate SRC
as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems.
Where a system clock exists at an integer multiple of the required ADC or DAC clock rate it is preferable to use this rather than
the PLL. The LM4935 is designed to work in 8, 12, 16, 24, 48 kHz modes from a 12 MHz clock and 8, 13, 26, 52 kHz modes from
a 13 MHz clock without the use of the PLL. This saves power and reduces clock jitter which can affect SNR.
The actual ADC and DAC sample rates are set up by the PLL and internal clock dividers.
LM4935
www.national.com
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