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| 型号： | WLA49VVA |
| 厂商： | National Semiconductor Corporation |
| 元件分类： | ADC |
| 英文描述： | Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC |
| 中文描述： | 音频子系统的双模单声道立体声耳机和扬声器放大器的高效率和多功能模数转换器 |
| 文件页数： | 21/112页 |
| 文件大小： | 5017K |
| 代理商： | WLA49VVA |
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11.0 System Control
Method 1. I
2C Compatible Interface
11.1 I
2C SIGNALS
In I
2C mode the LM4935 pin SCL is used for the I2C clock SCL and the pin SDA is used for the I2C data signal SDA. Both these
signals need a pull-up resistor according to I
2C specification. The I2C slave address for LM4935 is 0011010
2.
11.2 I
2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can
only be changed when SCL is LOW.
201341Q1
I
2C Signals: Data Validity
11.3 I
2C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of the I
2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH
while SCL is HIGH. The I
2C master always generates START and STOP bits. The I2C bus is considered to be busy after START
condition and free after STOP condition. During data transmission, I
2C master can generate repeated START conditions. First
START and repeated START conditions are equivalent, function-wise.
201341Q2
11.4 TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data
has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter
releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9
th clock
pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been
received.
After the START condition, the I
2C master sends a chip address. This address is seven bits long followed by an eighth bit which
is a data direction bit (R/W). The LM4935 address is 0011010
2. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a
READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected
register.
201341Q3
I
2C Chip Address
Register changes take an effect at the SCL rising edge during the last ACK from slave.
LM4935
www.national.com
16
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