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| 型号： | WLA49VVA |
| 厂商： | National Semiconductor Corporation |
| 元件分类： | ADC |
| 英文描述： | Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC |
| 中文描述： | 音频子系统的双模单声道立体声耳机和扬声器放大器的高效率和多功能模数转换器 |
| 文件页数： | 27/112页 |
| 文件大小： | 5017K |
| 代理商： | WLA49VVA |
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12.0 Status & Control Registers (Continued)
12.1 BASIC CONFIGURATION REGISTER
This register is used to control the basic function of the chip.
TABLE 2. BASIC (0x00h)
Bits
Field
Description
1:0
CHIP_MODE
The LM4935 can be placed in one of four modes which dictate its basic operation. When a new
mode is selected the LM4935 will change operation silently and will re-configure the power
management profile automatically. The modes are described as follows:
CHIP MODE
Audio System
Detection System
Typical Application
00
2
Off
Power-down Mode
01
2
Off
On
Stand-by mode with headset event
detection
10
2
On
Off
Active without headset event detection
11
2
On
Active with headset event detection
2
PLL_ENABLE
If set the PLL can be used.
3
USE_OSC
If set the power management and control circuits will assume that no external clock is available and
will resort to using an on-chip oscillator for SAR, headset detection and analog power management
functions such as click and pop.
5:4
CAP_SIZE
Programs the extra delays required to stabilize once charge/discharge is complete, based on the size
of the bypass capacitor.
CAP_SIZE
Bypass Capacitor Size
Turn-off/on time
00
2
0.1 F
45 ms/75 ms
01
2
1 F
45 ms/140 ms
10
2
2.2 F
45 ms/260 ms
11
2
4.7 F
45 ms/500 ms
6
STEREO
If set, the mixers assume that the signals on the left and right internal busses are highly correlated
and when these signals are combined their levels are reduced by 6 dB to allow enough headroom for
them to be summed at the Loudspeaker, Earpiece, CPOUT, and AUXOUT amplifiers. For the
Headphone amplifier, if this bit is set, the left and right signal levels are routed to the corresponding
left or right headphone output; if this bit is cleared, the left and the right signals are added and routed
to both headphone outputs and their levels are reduced by 6dB to allow enough headroom.
7
OCL
If set the part is placed in OCL (Output Capacitor Less) mode.
For reliable headset / push button detection the following bits should be defined before enabling the headset detection system by
setting bit 0 of CHIP_MODE:
The OCL-bit (Cap / Capless headphone interface; bit 7 of this register)
The headset insert/removal debounce settings (bits 6:3 of DETECT (0x17h))
The BTN_TYPE-bit (Parallel / Series push button type; bit 3 MIC_2 register (0x0Ch))
The parallel push button debounce settings (bits 5:4 of MIC_2 register (0x0Ch))
All register fields controlling the audio system should be defined before setting bit 1 of CHIP_MODE and should not be altered
while the audio sub-system is active.
If the analog or digital levels are below 12 dB then it is not necessary to set the stereo bit allowing greater output levels to be
obtained for such signals.
LM4935
www.national.com
21
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