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| 型号： | WLA49VVA |
| 厂商： | National Semiconductor Corporation |
| 元件分类： | ADC |
| 英文描述： | Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC |
| 中文描述： | 音频子系统的双模单声道立体声耳机和扬声器放大器的高效率和多功能模数转换器 |
| 文件页数： | 70/112页 |
| 文件大小： | 5017K |
| 代理商： | WLA49VVA |
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12.0 Status & Control Registers (Continued)
12.37 SAR OVERVIEW
The SAR controller works via a scheduler that allocates time slots for each of the four channels. All four channels can operate up
to the same maximum frequency. When the sampling frequency of a channel is to be reduced the time slot allocated to that
channel is simply enabled less often. For example if one slot is to work at a quarter of the frequency of the others then only one
in four of its allocated slot triggers the SAR to activate:
Each time slot is used to sample a single fixed input, slot 0 is used for VSAR 1, slot 1 for VSAR 2, slot 2 for either D_V
DD or
BB_V
DD* and slot 3 for the A_VDD. When a particular time slot is activated the correct mux, clock and enable controls to the ADC
module are produced and the output sampled when ready. If the D_V
DD or the A_VDD are being sampled then a voltage divider
is used to half the input to below the full scale reference of 2.5V. As this results in a current path to ground it is only inserted while
the ADC is settling to reduce power consumption.
Using this method, samples can be taken using as little power as possible while allowing sample rates as low as 1 Hz. The data
can either be read directly or used to trigger interrupts when set voltages are passed. This reduces the baseband controllers
software overhead and IO bandwidth, further reducing system power.
The full scale digital output from the SAR is equal to 2.5V. The A_V
DD and D_VDD inputs are divided by two during sampling. The
SAR ADC can be activated at any time, even while the chip is in shutdown mode (chip mode ’00’). This allows the LM4935 to
perform housekeeping duties such as voltage monitoring with minimal power consumption.
*Depending on SLOT_2_VBB in SAR_SLOT23 (0x1Ch).
20134118
FIGURE 13. Internal SAR Control Signals to SAR Module
LM4935
www.national.com
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