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| 型号： | WLA49VVA |
| 厂商： | National Semiconductor Corporation |
| 元件分类： | ADC |
| 英文描述： | Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC |
| 中文描述： | 音频子系统的双模单声道立体声耳机和扬声器放大器的高效率和多功能模数转换器 |
| 文件页数： | 29/112页 |
| 文件大小： | 5017K |
| 代理商： | WLA49VVA |
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12.0 Status & Control Registers (Continued)
12.3 LM4935 CLOCK NETWORK
The audio ADC operates at 125*fs, so it requires a 1.000 MHz clock to sample at 8 kHz (at point C as marked on the following
diagram). The stereo DAC operates at 250*fs, i.e. 12.000 MHz (at point B) for 48 kHz data. It is expected that the PLL is used
to drive the audio system unless a 12.000 MHz master clock is supplied and the sample rate is always a multiple of 8 kHz, in
which case the PLL can be bypassed to reduce power, clock division instead being performed by the Q and R dividers. The PLL
can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of the PLL and the audio
ADC either uses the PLL output divided by 2*FSDAC/FSADC or a system clock divided by Q, this allows n*8 kHz recording and
44.1 kHz playback.
MCLK must be less than or equal to 30 MHz, the I2S clock should be an integer multiple of the DAC’s sampling frequency and
should be below 6 MHz.
When using the Class D amplifier with the DAC the Class D clock generator will assume 12 MHz at point A, if this is not the case
then the DAC and power stage may become unsynchronized and SNR performance may be reduced.
The LM4935 is designed to work from a 12.000 MHz or 11.025 MHz clock at point A. This is used to drive the power management
and control logic. Performance may not meet the electrical specifications if the frequency at this point deviates significantly
beyond this range.
20134110
FIGURE 6. LM4935 Clock Network
LM4935
www.national.com
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