参数资料
| 型号： | X45620V20I-2.7 |
| 厂商： | Intersil |
| 文件页数： | 10/20页 |
| 文件大小： | 0K |
| 描述： | IC VOLT MON DUAL SW EEPR 20TSSOP |
| 标准包装： | 75 |
| 类型： | 多压监控器 |
| 监视电压数目： | 2 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 75 ms |
| 电压 - 阀值： | 1.75V，2.62V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
X45620
WDO Output Timing
Symbol
Parameter
Min
Typ (6)
Max
Unit
Test Conditions
t WDO
Watchdog Time Out Period,
WD1 = 1, WD0 = 0
75
150
250
ms
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
200
500
400
800
600
1200
ms
ms
Note 4
Note 4
t RST
Reset Time Out
75
150
250
ms
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X45620 activates a Power-
on Reset Circuit. This circuit goes active at about 1V
and pulls the RESET pin active. This signal prevents
the system microprocessor from starting to operate
with insufficient voltage or prior to stabilization of the
oscillator. When Vcc exceeds the device V TRIP1 value
for t PURST the circuit releases RESET, allowing the
processor to begin executing code.
Low V CC (V1MON) Voltage Monitoring
During operation, the X45620 monitors the V CC level
and asserts RESET if supply voltage falls below a pre-
set minimum V TRIP1 . During this time the communica-
tion to the device is interrupted. The RESET signal also
prevents the microprocessor from operating in a power
fail or brownout condition. The RESET signal remains
active until the voltage drops below 1V. RESET also
remains active until V CC returns and exceeds V TRIP1
for t PURST .
Low V2MON Voltage Monitoring
The X45620 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V TRIP2 . The V2FAIL signal is either ORed with
Figure 1. Two Uses of Dual Voltage Monitoring
V OUT
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V2FAIL signal remains active
until V2MON returns and exceeds V TRIP2 .
The V2MON circuit is powered by V CC (or V BATT ). If
both V CC and V BATT are at or below Vtrip, V2MON will
not be monitored.
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring SDA and SCL pin. In normal
operation, the microprocessor must periodically restart
the Watchdog Timer to prevent WDO from going
active. The watchdog timer is restarted on the first
HIGH to LOW transition on SCL after a start com-
mand. The start command is defined as SDA going
HIGH to LOW while SCL is HIGH. The state of two
nonvolatile control bits in the Status Register deter-
mines the watchdog timer period. The microprocessor
can change these watchdog bits by writing to the sta-
tus register. The factory default setting disables the
watchdog timer.
The Watchdog Timer oscillator stops and resets when
in battery backup mode. It re-starts when V CC returns.
V OUT
X45620
X45620
Unregulated
Supply
R1
5V
Reg
V CC
RESET
System
Reset
Unregulated
Supply
5V
Reg
V CC
RESET
R2
V2MON
V2FAIL
System
Interrupt
3.0V
Reg
V2MON
V2FAIL
System
Reset
R1 and R2 selected so V2 = V2MON threshold when
Unregulated supply reaches 6V.
10
Notice: No external components required to monitor
two voltages.
FN8250.0
July 29, 2005
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