参数资料
| 型号： | X45620V20I-2.7 |
| 厂商： | Intersil |
| 文件页数： | 11/20页 |
| 文件大小： | 0K |
| 描述： | IC VOLT MON DUAL SW EEPR 20TSSOP |
| 标准包装： | 75 |
| 类型： | 多压监控器 |
| 监视电压数目： | 2 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 75 ms |
| 电压 - 阀值： | 1.75V，2.62V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
X45620
System Battery Switch
As long as V CC exceeds the low voltage detect thresh-
old V TRIP1 , V OUT is connected to V CC through a 5 ?
(typical) switch. When the V CC has fallen below V TRIP ,
Operation
The device is in normal operation with V CC as long as
V CC > V TRIP1 . It switches to the battery backup mode
when V CC goes away.
then V CC is applied to V OUT if V CC is equal to or
greater than V BATT + 0.03V. When V CC drops to less
than V BATT - 0.03V, then V OUT is connected to V BATT
through an 80 ? (typical) switch. V OUT typically sup-
plies the system static RAM voltage, so the switchover
circuit operates to protect the contents of the static
RAM during a power failure. Typically, when V CC has
failed, the SRAMs go into a lower power state and
draw much less current than in their active mode.
Condition
V CC > V TRIP1
V CC > V TRIP1 &
V BATT = 0
0 ≤ V CC < V TRIP1
and V CC < V BATT
Mode of Operation
Normal Operation.
Normal Operation without battery
back up capability.
Battery Backup Mode; RESET
signal is asserted. No communica-
tion to the device is allowed.
When V CC returns, V OUT switches back to V CC when
V CC exceeds V BATT +0.03V. There is a 60mV hystere-
sis around this battery switch threshold to prevent
oscillations between supplies.
While V CC is connected to V OUT the BATT-ON pin is
pulled LOW. The signal can drive external pass ele-
ments to provide additional current to the external cir-
cuits during normal operation.
Manual Reset
By connecting a push-button from MR to ground or
driven by logic, the designer adds manual system reset
capability. The RESET pins is asserted when the push-
button is closed and remain asserted for t PURST after the
push-button is released. This pin is debounced so a
push-button connected directly to the device will have
both clean falling and rising edges on MR.
Figure 2. Example System Connection
Dual P-channel FET
Examples: IRF 7756, FDS9733A
Unregulated
Supply
5V
Reg
V CC
BATT-ON
SRAM
V OUT
V BATT
Address
V2MON
Decode
V2MON
Supercap
+
V2FAIL
Enable
NMI
Addr
V CC
Provides
Early Detection
of Power Failure
11
V SS
RESET
SDA, SCL
RESET
2-Wire μC
FN8250.0
July 29, 2005
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