参数资料
型号: X45620V20I-2.7
厂商: Intersil
文件页数: 15/20页
文件大小: 0K
描述: IC VOLT MON DUAL SW EEPR 20TSSOP
标准包装: 75
类型: 多压监控器
监视电压数目: 2
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 75 ms
电压 - 阀值: 1.75V,2.62V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 管件
X45620
The master terminates the data byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. Refer to Figure 12 for the address,
acknowledge, and data transfer sequence.
Stop and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the device will reset itself without
performing the write. The contents of the array will not
be affected.
Acknowledge Polling
The maximum write cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a start condi-
tion followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the inter-
nal write cycle, then no ACK will be returned. If the
device has completed the internal write operation, an
ACK will be returned and the host can then proceed
with the read or write operation. Refer to Figure 13.
Figure 11. Byte Write Sequence
Signals from
the Master
S
T
A
R
T
Slave
Address
Word Address
Byte 1
Word Address
Byte 0
Data
S
T
O
P
SDA Bus
S 1 0 1 0 0 S 1 S 0 0
P
A
A
A
A
Signals from
the Slave
C
K
C
K
C
K
C
K
Figure 12. Page Write Sequence
(0 ≤ n ≤ 64)
S
Signals from
the Master
T
A
R
T
Slave
Address
Word Address
Byte 1
Word Address
Byte 0
Data
(0)
Data
(n)
S
T
O
P
SDA Bus
S 1 0 1 0 0 S 1 S 0 0
P
Signals from
the Slave
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
15
FN8250.0
July 29, 2005
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