参数资料
| 型号： | X45620V20I-2.7 |
| 厂商： | Intersil |
| 文件页数： | 3/20页 |
| 文件大小： | 0K |
| 描述： | IC VOLT MON DUAL SW EEPR 20TSSOP |
| 标准包装： | 75 |
| 类型： | 多压监控器 |
| 监视电压数目： | 2 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 75 ms |
| 电压 - 阀值： | 1.75V，2.62V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
X45620
PIN DESCRIPTION (Continued)
Pin
8
9
10
11
14
12–13
15
16
17
18
19
20
Name
RESET
/MR
WDO
V SS
SDA
SCL
NC
V BATT
V OUT
BATT-ON
NC
WP
V CC
(V1MON)
Function
Reset Output/Manual Reset Input . This is an Input/Output pin.
RESET Output . This is an active LOW, open drain output which goes active whenever V CC falls
below the minimum V CC sense level. When RESET is active communication to the device is i nterrupt -
ed. RESET remains active until V CC rises above the minimum V CC sense level for t PURST . RESET
also goes active on power-up and remains active for t PURST after the power supply stabilizes.
MR Input . This is an active LOW debounced input. When MR is active, the RESET pins are assert-
ed. When MR is released, the RESET remains asserted for t PURST , and then released.
Watchdog Output. WDO is an active low, open drain output which goes active whenever the
watchdog timer goes active. WDO remains active for 150ms, then returns to the inactive state.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It is an open
drain output, requires the use of a pull-up resistor.
Serial Clock. The SCL input is used to clock all data into and out of the device.
No internal connections
Battery Supply Voltage. This input provides a backup supply in the event of a failure of the pri-
mary V CC voltage. The V BATT voltage typically provides the supply voltage necessary to maintain
the contents of SRAM and also powers the internal logic to “stay awake.” If unused, connect V BATT
to ground.
Output Voltage.
V OUT = V CC if V CC > V TRIP1 .
IF V CC < V TRIP1 , then,
V OUT = V CC if V CC > V BATT +0.03
V OUT = V BATT if V CC < V BATT -0.03
Note: There is hysteresis around V BATT ± 0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1μF must be connected to Vout to ensure stability.
Battery On. This CMOS output goes HIGH when the V OUT switches to V BATT and goes LOW
when V OUT switches to V CC . It is used to drive a external P-channel FET when V CC = V OUT and
current requirements are greater than 50mA.
The purpose of this output is to drive an external FET to get higher operating currents when the
V CC supply is fully functional. In the event of a V CC failure, the battery voltage is applied to the
V OUT pin and the external transistor is turned off. In this “backup condition,” the battery only needs
to supply enough voltage and current to keep SRAM devices from losing their data-there is no
communication at this time.
No Connect
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits. This pin has an internal pull down
resistor. (>10M ? typical)
Supply Voltage/V1 Voltage Monitor Input. When the V1MON input is less than the VTRIP1
voltage, RESET and LOWLINE go ACTIVE.
3
FN8250.0
July 29, 2005
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