参数资料
| 型号： | X96012V14IZT1 |
| 厂商： | Intersil |
| 文件页数： | 18/23页 |
| 文件大小： | 0K |
| 描述： | IC BIAS CTRLR UNIV SNSR 14-TSSOP |
| 标准包装： | 2,500 |
| 类型： | 传感器调节器 |
| 输入类型： | 电压 |
| 输出类型： | 电压 |
| 接口： | 2 线 |
| 电流 - 电源： | 15mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
4
FN8216.3
February 20, 2008
IR
Current from pin R1 or R2 to VSS
0
3200
A
VPOR
Power-on Reset Threshold
Voltage
1.5
2.8
V
VCCRamp
VCC Ramp Rate
0.2
50
mV/s
VADCOK
ADC Enable Minimum Voltage
Figure 11
2.6
2.8
V
NOTES:
2. These parameters are periodically sampled and not 100% tested.
3. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
4. The device goes into Standby: 200ns after any STOP, except those that initiate a nonvolatile write cycle. It goes into Standby tWC after a STOP
that initiates a nonvolatile write cycle. It also goes into Standby 9 clock cycles after any START that is not followed by the correct Slave Address
Byte.
5. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
6. For this range of V(VREF) the full scale sink mode current at I1 and I2 follows V(VREF) with a linearity error smaller than 1%.
7. These parameters are periodically sampled and not 100% tested.
8. TCOref = [Max V(VREF) - Min V(VREF)] x 106/(1.21V x +140°C).
Electrical Specifications
Conditions are as follows, unless otherwise specified. All typical values are for TA = +25°C and 5V at pin VCC.
Maximum and minimum specifications are over the recommended operating conditions. All voltages are
referred to the voltage at pin VSS. All bits in control registers are “0”. 255Ω, 0.1%, resistor connected between
R1 and VSS, and another between R2 and VSS. 400kHz TTL input at SCL. SDA pulled to VCC through an
external 2k
Ω resistor. 2-wire interface in “standby” (see Notes 9 and 10 on page 5). WP, A0, A1, and A2 floating.
VREF pin unloaded. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
D/A Converter Characteristics (See “Electrical Specifications” table starting on page 3 for standard conditions).
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
IFS00
I1 or I2 Full Scale Current, with External Resistor
Setting
(Notes 9, 12)
1.56
1.58
1.6
mA
3.2
mA
IFS01
I1 or I2 Full Scale Current, with Internal Low
Current Setting Option
DAC input Byte = FFh,
Source or sink mode, V(I1) and V(I2)
are VCC - 1.2V in source mode and
1.2V in sink mode.
(Notes 10, 11)
0.3
0.4
0.5
mA
IFS10
I1 or I2 Full Scale Current, with Internal Middle
Current Setting Option
0.64
0.85
1.06
mA
IFS11
I1 or I2 Full Scale Current, with Internal High
Current Setting Option
11.3
1.6
mA
OffsetDAC
I1 or I2 D/A Converter Offset Error
1
LSB
FSErrorDAC
I1 or I2 D/A Converter Full Scale Error
-2
2
LSB
DNLDAC
I1 or I2 D/A Converter Differential Nonlinearity
-0.5
0.5
LSB
INLDAC
I1 or I2 D/A Converter Integral Nonlinearity with
Respect to a Straight Line Through 0 and the Full
Scale Value
-1
1
LSB
VISink
I1 or I2 Sink Voltage Compliance
(Note 12)
1.2
VCC
V
2.5
VCC
V
VISource
I1 or I2 Source Voltage Compliance
(Note 12)
0
VCC - 1.2
V
0
VCC - 2.5
V
X96012
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