参数资料
| 型号： | X96012V14IZT1 |
| 厂商： | Intersil |
| 文件页数： | 19/23页 |
| 文件大小： | 0K |
| 描述： | IC BIAS CTRLR UNIV SNSR 14-TSSOP |
| 标准包装： | 2,500 |
| 类型： | 传感器调节器 |
| 输入类型： | 电压 |
| 输出类型： | 电压 |
| 接口： | 2 线 |
| 电流 - 电源： | 15mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
5
FN8216.3
February 20, 2008
.
IOVER
I1 or I2 Overshoot on D/A Converter Data Byte
Transition
DAC input byte changing from 00h to
FFh and vice versa, V(I1) and V(I2)
are VCC - 1.2V in source mode and
1.2V in sink mode. (Note 2)
0A
IUNDER
I1 or I2 Undershoot on D/A Converter Data Byte
Transition
0A
trDAC
I1 or I2 Rise Time on D/A Converter Data Byte
Transition; 10% to 90%
530
s
TCOI1I2
Temperature Coefficient of Output Current I1 or
I2 when Using Internal Resistor Setting
Bits I1FSO[1:0] 002 or
Bits I2FSO[1:0] 002,
VRMbit = “1”
See Figure 8
±200
ppm/°C
NOTES:
9. DAC input Byte = FFh, Source or sink mode.
10. LSB is defined as
divided by the resistance between R1 or R2 to VSS.
11. OffsetDAC: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is expressed in
LSB. FSErrorDAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It is
expressed in LSB. The OffsetDAC is subtracted from the measured value before calculating FSErrorDAC.DNLDAC: The Differential Non-Linearity of
a DAC is defined as the deviation between the measured and ideal incremental change in the output of the DAC, when the input changes by one
code step. It is expressed in LSB. The measured values are adjusted for Offset and Full Scale Error before calculating DNLDAC. INLDAC: The
Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjusting the measured transfer
curve for Offset and Full Scale Error. It is expressed in LSB.
12. V(I1) and V(I2) are VCC - 1.2V in source mode and 1.2V in sink mode. In this range the current at I1 or I2 varies < 1%.
13. The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum VCC = 4.5V. The compliance
voltage changes to 2.5V from the sourcing rail, and the current variation is < 1%.
D/A Converter Characteristics (See “Electrical Specifications” table starting on page 3 for standard conditions). (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
2
3
V(VRef)
255
x
[]
A/D Converter Characteristics (See “Electrical Specifications” table starting on page 3 for standard conditions).
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
ADCTIME
A/D Converter Conversion Time
Proportional to A/D converter input voltage.
This value is maximum at full scale input of
A/D converter. ADCfiltOff = “1”
9ms
RINADC
VSense Pin Input Resistance
VSense as an input, ADCIN bit = “1”
100
k
Ω
CINADC
VSense Pin Input Capacitance
VSense as an input, ADCIN bit = “1”,
Frequency = 1 MHz. (Note 2)
17
pF
VINADC
VSense Input Signal Range
This is the A/D Converter Dynamic
Range. ADCIN bit = “1”
0V(VRef)
V
THE ADC IS MONOTONIC
OffsetADC
A/D Converter Offset Error
±1
LSB
FSErrorADC
A/D Converter Full Scale Error
±1
LSB
DNLADC
A/D Converter Differential
Nonlinearity
±0.5
LSB
INLADC
A/D Converter Integral Nonlinearity
±1
LSB
TempStepADC
Temperature Step Causing One
Step Increment of ADC Output
(Note 2)
0.52
0.55
0.58
°C
Out25ADC
ADC Output at +25°C
011101012
X96012
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