参数资料
| 型号： | X96012V14IZT1 |
| 厂商： | Intersil |
| 文件页数： | 6/23页 |
| 文件大小： | 0K |
| 描述： | IC BIAS CTRLR UNIV SNSR 14-TSSOP |
| 标准包装： | 2,500 |
| 类型： | 传感器调节器 |
| 输入类型： | 电压 |
| 输出类型： | 电压 |
| 接口： | 2 线 |
| 电流 - 电源： | 15mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
14
FN8216.3
February 20, 2008
Look-Up Tables
The X96012 memory array contains two 64-byte look-up
tables. One is associated to pin I1’s output current generator
and the other to pin I2’s output current generator, through
their corresponding D/A converters. The output of each
look-up table is the byte contained in the selected row. By
default these bytes are the inputs to the D/A converters
driving pins I1 and I2.
The byte address of the selected row is obtained by adding
the look-up table base address (90h for LUT1, and D0h for
LUT2) and the appropriate row selection bits. See Figure 9.
By default, the look-up table selection bits are the 6
MSBs of the A/D converter output. Alternatively, the A/D
converter can be bypassed and the six row selection bits
are the six LSBs of Control Registers 1 and 2, for the
LUT1 and LUT2 respectively. The selection between
these options is illustrated in Figure 10, and described in
Current Generator Block
The Current Generator pins I1 and I2 are outputs of two
independent current mode D/A converters.
D/A Converter Operation
The Block Diagram for each of the D/A converters is shown
in Figure 8.
The input byte of the D/A converter selects a voltage on the
non-inverting input of an operational amplifier. The output of
the amplifier drives the gate of a FET, whose source is
connected to ground via resistor R1 or R2. This node is also
fed back to the inverting input of the amplifier. The drain of
the FET is connected to the output current pin (I1 or I2) via a
“polarity select” circuit block.
+
-
I1 OR I2 PIN
R1 OR R2 PIN
R1_EXTERNAL OR R2_EXTERNAL
I1DS OR I2DS: BITS
VSS
I1FSO[1:0]
R1
_LOW_CURRENT
OR
R1
_MIDDLE_
CU
RRE
N
T
OR
R1
_HIGH_CURR
E
N
T
OR
VREF
OPTIONAL EXTERNAL RESISTOR
SELECT
CIRCUIT
POLARITY
VCC
VOLTAGE
6 OR 7 IN CONTROL
REGISTER 0.
DIVIDER
DAC1 OR
DAC2
INPUT BYTE
VSS
OR I2FSO[1:0]
BITS 1 AND 0, OR
3 AND 2 IN CONTROL
REGISTER 5
11
10
01
00
R2
_HIGH_CURR
E
N
T
R2
_MIDDLE_
CU
RRE
N
T
R2
_LOW_CURRENT
FIGURE 8. D/A CONVERTER BLOCK DIAGRAM
X96012
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