参数资料
| 型号： | X96012V14IZT1 |
| 厂商： | Intersil |
| 文件页数： | 21/23页 |
| 文件大小： | 0K |
| 描述： | IC BIAS CTRLR UNIV SNSR 14-TSSOP |
| 标准包装： | 2,500 |
| 类型： | 传感器调节器 |
| 输入类型： | 电压 |
| 输出类型： | 电压 |
| 接口： | 2 线 |
| 电流 - 电源： | 15mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
7
FN8216.3
February 20, 2008
Timing Diagrams
Nonvolatile WRITE Cycle Timing
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNITS
See Figure 3
5
10
ms
NOTES:
16. Cb = total capacitance of one bus line (SDA or SCL) in pF.
17. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
18. The minimum frequency requirement applies between a START and a STOP condition.
tSU:STO
tDH
tHIGH
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
SCL
SDA IN
SDA OUT
tF
tLOW
tBUF
tAA
tR
FIGURE 1. BUS TIMING
tHD:WP
SCL
SDA IN
WP
tSU:WP
CLK 1
START
STOP
FIGURE 2. WP PIN TIMING
X96012
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