参数资料
| 型号： | X96012V14IZT1 |
| 厂商： | Intersil |
| 文件页数： | 20/23页 |
| 文件大小： | 0K |
| 描述： | IC BIAS CTRLR UNIV SNSR 14-TSSOP |
| 标准包装： | 2,500 |
| 类型： | 传感器调节器 |
| 输入类型： | 电压 |
| 输出类型： | 电压 |
| 接口： | 2 线 |
| 电流 - 电源： | 15mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
6
FN8216.3
February 20, 2008
NOTES:
14. LSB” is defined as V(VRef)/255, “Full-Scale” is defined as V(VRef).
15. OffsetADC: For an ideal converter, the first transition of its transfer curve occurs at
above zero. Offset error is the amount of
deviation between the measured first transition point and the ideal point. FSErrorADC: For an ideal converter, the last transition of its transfer
curve occurs at
. Full-Scale Error is the amount of deviation between the measured last transition point and the ideal point,
after subtracting the Offset from the measured curve. DNLADC: DNL is defined as the difference between the ideal and the measured code
transitions for successive A/D code outputs expressed in LSBs. The measured transfer curve is adjusted for Offset and Full-scale errors before
calculating DNL. INLADC: The deviation of the measured transfer function of an A/D converter from the ideal transfer function. The INL error is
also defined as the sum of the DNL errors starting from code 00h to the code where the INL measurement is desired. The measured transfer
curve is adjusted for Offset and Full scale errors before calculating INL.
A/D Converter Characteristics (See “Electrical Specifications” table starting on page 3 for standard conditions).
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
0.5 x V(VRef)
255
[]
254.5 x V(VRef)
255
[]
2-Wire Interface AC Characteristics
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNITS
fSCL
SCL Clock Frequency
See “2-Wire Interface Test
Conditions” on page 6
1
(Note 18)
400
kHz
Pulse width Suppression Time at Inputs
50
ns
SCL Low to SDA Data Out Valid
900
ns
Time the Bus Free Before Start of New
Transmission
1300
ns
tLOW
Clock Low Time
1.3
1200
(Note 18)
s
tHIGH
Clock High Time
0.6
1200
(Note 18)
s
tSU:STA
Start Condition Set-up Time
600
ns
tHD:STA
Start Condition Hold Time
600
ns
tSU:DAT
Data In Set-up Time
100
ns
tHD:DAT
Data In Hold Time
0
s
tSU:STO
Stop Condition Set-up Time
600
ns
tDH
Data Output Hold Time
50
ns
SDA and SCL Rise Time
20 +0.1Cb
(Note 16)
300
ns
SDA and SCL Fall Time
20 +0.1Cb
(Note 16)
300
ns
WP Set-up Time
600
ns
WP Hold Time
600
ns
Cb (Note 2)
Capacitive Load for Each Bus Line
400
pF
2-Wire Interface Test Conditions
Input Pulse Levels
10% to 90% of VCC
Input Rise and Fall Times, between 10% and 90%
10ns
Input and Output Timing Threshold Level
1.4V
External Load at Pin SDA
2.3k
Ω to V
CC and 100pF to VSS
X96012
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