参数资料
型号: XA3S1400A-4FGG484I
厂商: Xilinx Inc
文件页数: 30/57页
文件大小: 0K
描述: IC FPGA SPARTAN3A 1400K 484-FBGA
标准包装: 60
系列: Spartan®-3A XA
LAB/CLB数: 2816
逻辑元件/单元数: 25344
RAM 位总计: 589824
输入/输出数: 375
门数: 1400000
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 484-BBGA
供应商设备封装: 484-FBGA
XA Spartan-3A Automotive FPGA Family Data Sheet
DS681 (v2.0) April 22, 2011
Product Specification
36
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
22
LVDS_33
27
BLVDS_25
4
MINI_LVDS_25
22
MINI_LVDS_33
27
LVPECL_25
LVPECL_33
RSDS_25
22
RSDS_33
27
TMDS_33
27
PPDS_25
22
PPDS_33
27
DIFF_HSTL_I
–10
DIFF_HSTL_III
–4
DIFF_HSTL_I_18
8
DIFF_HSTL_II_18
–2
DIFF_HSTL_III_18
5
4
DIFF_SSTL18_I
3
7
DIFF_SSTL18_II
–4
DIFF_SSTL2_I
9
DIFF_SSTL2_II
–4
DIFF_SSTL3_I
4
5
DIFF_SSTL3_II
3
Notes:
1.
Not all I/O standards are supported on all I/O banks. The left and right banks (I/O banks 1 and 3) support higher output drive current than
the top and bottom banks (I/O banks 0 and 2). Similarly, true differential output standards, such as LVDS, RSDS, PPDS, miniLVDS, and
TMDS, are only supported in top or bottom banks (I/O banks 0 and 2). Refer to UG331: Spartan-3 Generation FPGA User Guide for
additional information.
2.
The numbers in this table are recommendations that assume sound board layout practice. Test limits are the VIL/VIH voltage limits for the
respective I/O standard.
3.
If more than one signal standard is assigned to the I/Os of a given bank, refer to XAPP689: Managing Ground Bounce in Large FPGAs for
information on how to perform weighted average SSO calculations.
Table 28: Recommended Number of Simultaneously Switching Outputs per VCCO/GND Pair (VCCAUX=3.3V) (Cont’d)
Signal Standard (IOSTANDARD)
Package Type: FTG256, FGG400, FGG484
Top, Bottom (Banks 0,2)
Left, Right (Banks 1,3)
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