参数资料
| 型号： | XA3S1400A-4FGG484I |
| 厂商： | Xilinx Inc |
| 文件页数： | 33/57页 |
| 文件大小： | 0K |
| 描述： | IC FPGA SPARTAN3A 1400K 484-FBGA |
| 标准包装： | 60 |
| 系列： | Spartan®-3A XA |
| LAB/CLB数： | 2816 |
| 逻辑元件/单元数： | 25344 |
| RAM 位总计： | 589824 |
| 输入/输出数： | 375 |
| 门数： | 1400000 |
| 电源电压： | 1.14 V ~ 1.26 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 484-BBGA |
| 供应商设备封装： | 484-FBGA |
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XA Spartan-3A Automotive FPGA Family Data Sheet
DS681 (v2.0) April 22, 2011
Product Specification
39
Clock Buffer/Multiplexer Switching Characteristics
18 x 18 Embedded Multiplier Timing
Table 32: Clock Distribution Switching Characteristics
Symbol
Description
Speed Grade: -4
Units
Min
Max
TGIO
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay
–0.23
ns
TGSI
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs.
Same as BUFGCE enable CE-input
–0.63
ns
FBUFG
Frequency of signals distributed on global buffers (all sides)
0
333
MHz
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8.
Table 33: 18 x 18 Embedded Multiplier Timing
Symbol
Description
Speed Grade: -4
Units
Min
Max
Combinatorial Delay
TMULT
Combinational multiplier propagation delay from the A and B inputs to the P
outputs, assuming 18-bit inputs and a 36-bit product (AREG, BREG, and
PREG registers unused)
–4.88
ns
Clock-to-Output Times
TMSCKP_P
Clock-to-output delay from the active transition of the CLK input to valid data
appearing on the P outputs when using the PREG register(2,3)
–1.30
ns
TMSCKP_A
TMSCKP_B
Clock-to-output delay from the active transition of the CLK input to valid data
appearing on the P outputs when using either the AREG or BREG register(2,4)
–4.97
ns
Setup Times
TMSDCK_P
Data setup time at the A or B input before the active transition at the CLK
when using only the PREG output register (AREG, BREG registers
unused)(3)
3.98
–ns
TMSDCK_A
Data setup time at the A input before the active transition at the CLK when
using the AREG input register(4)
0.00
–ns
TMSDCK_B
Data setup time at the B input before the active transition at the CLK when
using the BREG input register(4)
0.00
–ns
Hold Times
TMSCKD_P
Data hold time at the A or B input after the active transition at the CLK when
using only the PREG output register (AREG, BREG registers unused)(3)
0.00
–ns
TMSCKD_A
Data hold time at the A input after the active transition at the CLK when using
the AREG input register(4)
0.45
–ns
TMSCKD_B
Data hold time at the B input after the active transition at the CLK when using
the BREG input register(4)
0.45
–ns
Clock Frequency
FMULT
Internal operating frequency for a two-stage 18x18 multiplier using the AREG
and BREG input registers and the PREG output register(1)
0
250
MHz
Notes:
1.
Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
2.
The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
3.
The PREG register is typically used when inferring a single-stage multiplier.
4.
Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
5.
The numbers in this table are based on the operating conditions set forth in Table 8.
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