参数资料
| 型号： | XA3S1400A-4FGG484I |
| 厂商： | Xilinx Inc |
| 文件页数： | 36/57页 |
| 文件大小： | 0K |
| 描述： | IC FPGA SPARTAN3A 1400K 484-FBGA |
| 标准包装： | 60 |
| 系列： | Spartan®-3A XA |
| LAB/CLB数： | 2816 |
| 逻辑元件/单元数： | 25344 |
| RAM 位总计： | 589824 |
| 输入/输出数： | 375 |
| 门数： | 1400000 |
| 电源电压： | 1.14 V ~ 1.26 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 484-BBGA |
| 供应商设备封装： | 484-FBGA |
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XA Spartan-3A Automotive FPGA Family Data Sheet
DS681 (v2.0) April 22, 2011
Product Specification
41
Digital Clock Manager Timing
For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency
Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB
inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table 35
and Table 36) apply to any application that only employs the DLL component. When the DFS and/or the PS components are
used together with the DLL, then the specifications listed in the DFS and PS tables (Table 37 through Table 40) supersede
any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions
Period jitter and cycle-cycle jitter are two of many different ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Period jitter is the worst-case deviation from the ideal clock period over a collection of millions of samples. In a histogram of
period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods
sampled. In a histogram of cycle-cycle jitter, the mean value is zero.
Delay-Locked Loop
Table 35: Recommended Operating Conditions for the DLL
Symbol
Description
Speed Grade: -4
Units
Min
Max
Input Frequency Ranges
FCLKIN
CLKIN_FREQ_DLL
Frequency of the CLKIN clock input
5(2)
250(3)
MHz
Input Pulse Requirements
CLKIN_PULSE
CLKIN pulse width as a percentage of
the CLKIN period
FCLKIN 150 MHz
40%
60%
–
FCLKIN 150 MHz
45%
55%
–
Input Clock Jitter Tolerance and Delay Path Variation(4)
CLKIN_CYC_JITT_DLL_LF
Cycle-to-cycle jitter at the CLKIN
input
FCLKIN 150 MHz
–
±300
ps
CLKIN_CYC_JITT_DLL_HF
FCLKIN 150 MHz
–
±150
ps
CLKIN_PER_JITT_DLL
Period jitter at the CLKIN input
–±1
ns
CLKFB_DELAY_VAR_EXT
Allowable variation of off-chip feedback delay from the DCM
output to the CLKFB input
–±1
ns
Notes:
1.
DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2.
The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 37.
3.
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock period by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
4.
CLKIN input jitter beyond these limits might cause the DCM to lose lock.
5.
The DCM specifications are guaranteed when both adjacent DCMs are locked.
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