参数资料
| 型号： | XC2S100-5FGG256C |
| 厂商： | Xilinx Inc |
| 文件页数： | 12/99页 |
| 文件大小： | 0K |
| 描述： | IC SPARTAN-II FPGA 100K 256-FBGA |
| 标准包装： | 90 |
| 系列： | Spartan®-II |
| LAB/CLB数： | 600 |
| 逻辑元件/单元数： | 2700 |
| RAM 位总计： | 40960 |
| 输入/输出数： | 176 |
| 门数： | 100000 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 256-BGA |
| 供应商设备封装： | 256-FBGA（17x17） |
| 其它名称： | 122-1302 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页当前第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页
DS001-1 (v2.8) June 13, 2008
Module 1 of 4
Product Specification
2
2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
Introduction
The Spartan-II Field-Programmable Gate Array family
gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
six-member family offers densities ranging from 15,000 to
200,000 system gates, as shown in Table 1. System
performance is supported up to 200 MHz. Features include
block RAM (to 56K bits), distributed RAM (to 75,264 bits),
16 selectable I/O standards, and four DLLs. Fast,
predictable interconnect means that successive design
iterations continue to meet timing requirements.
The Spartan-II family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial
cost, lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
Second generation ASIC replacement technology
-
Densities as high as 5,292 logic cells with up to
200,000 system gates
-
Streamlined features based on Virtex FPGA
architecture
-
Unlimited reprogrammability
-
Very low cost
-
Cost-effective 0.18 micron process
System level features
-
SelectRAM hierarchical memory:
16 bits/LUT distributed RAM
Configurable 4K bit block RAM
Fast interfaces to external RAM
-
Fully PCI compliant
-
Low-power segmented routing architecture
-
Full readback ability for verification/observability
-
Dedicated carry logic for high-speed arithmetic
-
Efficient multiplier support
-
Cascade chain for wide-input functions
-
Abundant registers/latches with enable, set, reset
-
Four dedicated DLLs for advanced clock control
-
Four primary low-skew global clock distribution
nets
-
IEEE 1149.1 compatible boundary scan logic
Versatile I/O and packaging
-
Pb-free package options
-
Low-cost packages available in all densities
-
Family footprint compatibility in common packages
-
16 high-performance interface standards
-
Hot swap Compact PCI friendly
-
Zero hold time simplifies system timing
Core logic powered at 2.5V and I/Os powered at 1.5V,
2.5V, or 3.3V
Fully supported by powerful Xilinx ISE development
system
-
Fully automatic mapping, placement, and routing
6
Spartan-II FPGA Family:
Introduction and Ordering
Information
DS001-1 (v2.8) June 13, 2008
0
Product Specification
R
Table 1: Spartan-II FPGA Family Members
Device
Logic
Cells
System Gates
(Logic and RAM)
CLB
Array
(R x C)
Total
CLBs
Maximum
Available
User I/O(1)
Total
Distributed RAM
Bits
Total
Block RAM
Bits
XC2S15
432
15,000
8 x 12
96
86
6,144
16K
XC2S30
972
30,000
12 x 18
216
92
13,824
24K
XC2S50
1,728
50,000
16 x 24
384
176
24,576
32K
XC2S100
2,700
100,000
20 x 30
600
176
38,400
40K
XC2S150
3,888
150,000
24 x 36
864
260
55,296
48K
XC2S200
5,292
200,000
28 x 42
1,176
284
75,264
56K
Notes:
1.
All user I/O counts do not include the four global clock/user input pins. See details in Table 2, page 4.
相关PDF资料 |
PDF描述 |
|---|---|
| AMM24DTBT | CONN EDGECARD 48POS R/A .156 SLD |
| AMM24DTAT | CONN EDGECARD 48POS R/A .156 SLD |
| AMC31DRXS-S734 | CONN EDGECARD 62POS DIP .100 SLD |
| ABC60DRXN-S734 | CONN EDGECARD 120PS DIP .100 SLD |
| ABC60DRXH-S734 | CONN EDGECARD 120PS DIP .100 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC2S100-5FGG256I | 功能描述:IC SPARTAN-II FPGA 100K 256-FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-II 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA（27x27） |
| XC2S100-5FGG456C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S100-5FGG456I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S100-5PQ208C | 功能描述:IC FPGA 2.5V 600 CLB'S 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-II 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA（27x27） |
| XC2S1005PQ208I | 制造商:Xilinx 功能描述: |
发布紧急采购，3分钟左右您将得到回复。