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| 型号： | XC5204-6PQ240C |
| 厂商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays |
| 中文描述： | 现场可编程门阵列 |
| 文件页数： | 30/73页 |
| 文件大小： | 598K |
| 代理商： | XC5204-6PQ240C |
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R
XC5200 Series Field Programmable Gate Arrays
7-118
November 5, 1998 (Version 5.2)
Synchronous Peripheral Mode
Synchronous Peripheral mode can also be considered
Slave Parallel mode. An external signal drives the CCLK
input(s) of the FPGA(s). The first byte of parallel configura-
tion data must be available at the Data inputs of the lead
FPGA a short setup time before the rising CCLK edge.
Subsequent data bytes are clocked in on every eighth con-
secutive rising CCLK edge.
The same CCLK edge that accepts data, also causes the
RDY/BUSY output to go High for one CCLK period. The pin
name is a misnomer. In Synchronous Peripheral mode it is
really an ACKNOWLEDGE signal. Synchronous operation
does not require this response, but it is a meaningful signal
for test purposes. Note that RDY/BUSY is pulled High with
a high-impedance pullup prior to INIT going High.
The lead FPGA serializes the data and presents the pre-
amble data (and all data that overflows the lead device) on
its DOUT pin. There is an internal delay of 1.5 CCLK peri-
ods, which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
In order to complete the serial shift operation, 10 additional
CCLK rising edges are required after the last data byte has
been loaded, plus one more CCLK cycle for each
daisy-chained device.
Synchronous Peripheral mode is selected by a <011> on
the mode pins (M2, M1, M0).
X9005
CONTROL
SIGNALS
DATA BUS
PROGRAM
DOUT
M0 M1
M2
D0-7
INIT
DONE
PROGRAM
4.7 k
3.3 k
3.3 k
RDY/BUSY
VCC
OPTIONAL
DAISY-CHAINED
FPGAs
NOTE:
M2 can be shorted to Ground
if not used as I/O
CCLK
CLOCK
PROGRAM
DOUT
XC5200E/EX
SLAVE
M0 M1
N/C
8
M2
DIN
INIT
DONE
CCLK
N/C
XC5200
SYNCHRO-
NOUS
PERIPHERAL
Figure 33: Synchronous Peripheral Mode Circuit Diagram
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相关代理商/技术参数 |
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| XC5204-6PQG160C | 制造商:Xilinx 功能描述:XC5204-6PQG160C, FPGA XC5200 FAMILY 6K GATES 480 CELLS - Trays 制造商:Xilinx 功能描述:Xilinx XC5204-6PQG160C, FPGA XC5200 Family 6K Gates 480 Cells 83MHz 0.5um (CMOS) Technology 5V 160-Pin PQFP |
| XC5204-6TQ144C | 功能描述:IC FPGA 120 CLB'S 144-TQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC5200 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| XC5204-6TQ144I | 制造商:Xilinx 功能描述: |
| XC5204-6TQ176C | 制造商:XILINX 制造商全称:XILINX 功能描述:Field Programmable Gate Arrays |
| XC5204-6VQ100C | 功能描述:IC FPGA 120 CLB'S 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:XC5200 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
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