参数资料
型号: XC5204-6PQ240C
厂商: Xilinx, Inc.
英文描述: Field Programmable Gate Arrays
中文描述: 现场可编程门阵列
文件页数: 69/73页
文件大小: 598K
代理商: XC5204-6PQ240C
R
November 5, 1998 (Version 5.2)
7-153
XC5200 Series Field Programmable Gate Arrays
7
Additional No Connect (N.C.) Connections for HQ208 and HQ240 Packages
Notes: * Pins labeled VCC* are internally bonded to a VCC plane within the BG225 and BG352 packages. The external pins for the
BG225 are: B2, D8, H15, R8, B14, R1, H1, and R15. The external pins for the BG352 are: A10, A17, B2, B25, D13, D19, D7,
G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC14, AC20, AC8, AE2, AE25, AF10, and AF17.
Pins labeled GND* are internally bonded to a ground plane within the BG225 and BG352 packages. The external pins for the
BG225 are: A1, D12, G7, G9, H6, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8. The external pins for the BG352 are:
A1, A2, A5, A8, A14, A19, A22, A25, A26, B1, B26, E1, E26, H1, H26, N1, P26, W1, W26, AB1, AB26, AE1, AE26, AF1,
AF13, AF19, AF2, AF22, AF25, AF26, AF5, AF8.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 1056 = BSCAN.UPD
235.
I/O
-
M5
-
B11
90
236.
I/O
-
P1
-
A11
93
237.
I/O (A4)
134
174
202
N1
A10
D12
99
238.
I/O (A5)
135
175
203
M3
D9
C12
102
239.
I/O
-
176
205
M2
C9
B12
105
240.
I/O
136
177
206
L5
B9
A12
111
241.
I/O
137
178
207
M1
A9
C13
114
242.
I/O
138
179
208
L4
E9
B13
117
243.
I/O (A6)
139
180
209
L3
C8
A13
126
244.
I/O (A7)
140
181
210
L2
B8
B14
129
GND
141
182
211
L1
GND*
-
HQ208
HQ240
206
102
219
207
104
22
208
105
37
1
107
83
3
155
98
51
156
143
52
157
158
53
158
204
54
-
Pin
Description
PQ160
HQ208
HQ240
PG299
BG225
BG352
Boundary Scan Order
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