MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor
73
Chapter 7
EEPROM
7.1 Introduction
The MC68HC812A4 EEPROM (electrically erasable, programmable, read-only memory) serves as a
4096-byte nonvolatile memory which can be used for frequently accessed static data or as fast access
program code. Operating system kernels and standard subroutines would benefit from this feature.
The MC68HC812A4 EEPROM is arranged in a 16-bit configuration. The EEPROM array may be read as
either bytes, aligned words, or misaligned words. Access times are one bus cycle for byte and aligned
word access and two bus cycles for misaligned word operations.
Programming is by byte or aligned word. Attempts to program or erase misaligned words will fail. Only the
lower byte will be latched and programmed or erased. Programming and erasing of the user EEPROM
can be done in all modes.
Each EEPROM byte or aligned word must be erased before programming. The EEPROM module
supports byte, aligned word, row (32 bytes), or bulk erase, all using the internal charge pump. Bulk
erasure of odd and even rows is also possible in test modes; the erased state is $FF. The EEPROM
module has hardware interlocks which protect stored data from corruption by accidentally enabling the
program/erase voltage. Programming voltage is derived from the internal VDD supply with an internal
charge pump. The EEPROM has a minimum program/erase life of 10,000 cycles over the complete
operating temperature range.
7.2 EEPROM Programmer’s Model
The EEPROM module consists of two separately addressable sections. The first is a 4-byte memory
mapped control register block used for control, testing and configuration of the EEPROM array. The
second section is the EEPROM array itself.
At reset, the 4-byte register section starts at address $00F0 and the EEPROM array is located from
addresses $1000 to $1FFF (see
Figure 7-1). For information on remapping the register block and
Read/write access to the memory array section can be enabled or disabled by the EEON control bit in the
INITEE register. This feature allows the access of memory mapped resources that have lower priority than
the EEPROM memory array. EEPROM control registers can be accessed and EEPROM locations may
be programmed or erased regardless of the state of EEON.
Using the normal EEPROG control, it is possible to continue program/erase operations during wait. For
lowest power consumption during wait, stop program/erase by turning off EEPGM.
If the stop mode is entered during programming or erasing, program/erase voltage is automatically turned
off and the RC clock (if enabled) is stopped. However, the EEPGM control bit remains set. When stop
mode is terminated, the program/erase voltage automatically turns back on if EEPGM is set.
At low bus frequencies, the RC clock must be turned on for program/erase.