Serial Peripheral Interface (SPI)
MC68HC812A4 Data Sheet, Rev. 7
182
Freescale Semiconductor
15.5 Functional Description
The SPI allows full-duplex, synchronous, serial communication between the MCU and peripheral devices,
including other MCUs. In master mode, the SPI generates the synchronizing clock and initiates
transmissions. In slave mode, the SPI depends on a master peripheral to start and synchronize
transmissions.
15.5.1 Master Mode
The SPI operates in master mode when the master mode bit, MSTR, is set.
NOTE
Configure SPI modules as master or slave before enabling them. Enable
the master SPI before enabling the slave SPI. Disable the slave SPI before
disabling the master SPI.
Only a master SPI module can initiate transmissions. Begin the transmission from a master SPI module
by writing to the SPI data register. If the shift register is empty, the byte immediately transfers to the shift
register. The byte begins shifting out on the master out, slave in pin (MOSI) under the control of the serial
As the byte shifts out on the MOSI pin, a byte shifts in from the slave on the master in, slave out pin (MISO)
pin. On the eighth serial clock cycle, the transmission ends and sets the SPI flag, SPIF. At the same time
that SPIF becomes set, the byte from the slave transfers from the shift register to the SPI data register.
The byte remains in a read buffer until replaced by the next byte from the slave.
Figure 15-3. Full-Duplex Master/Slave Connections
15.5.2 Slave Mode
The SPI operates in slave mode when MSTR is clear. In slave mode, the SCK pin is the input for the serial
clock from the master.
NOTE
Before a transmission occurs, the SS pin of the slave SPI must be at logic 0.
The slave SS pin must remain low until the transmission is complete.
A transmission begins when initiated by a master SPI. The byte from the master SPI begins shifting in on
the slave MOSI pin under the control of the master serial clock.
As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register. On the
eighth serial clock cycle, the transmission ends and sets the SPI flag, SPIF. At the same time that SPIF
SHIFT REGISTER
CLOCK
DIVIDER
MASTER MCU
SLAVE MCU
VDD
MOSI
MISO
SCK
SS