Serial Communications Interface Module (SCI)
MC68HC812A4 Data Sheet, Rev. 7
160
Freescale Semiconductor
14.5.4.2 Character Reception
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register
is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCSR1) becomes
set, indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control
register 2 (SCCR2) is also set, the RDRF flag generates an interrupt request.
14.5.4.3 Data Sampling
The receiver samples the RXD pin at the RT clock rate. The RT clock is an internal signal with a frequency
16 times the baud rate. To adjust for baud rate mismatch, the RT clock
(see Figure 14-6) is
resynchronized:
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three
logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
Figure 14-6. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table14-4 summarizes the results of the start bit verification samples.
Table 14-4. Start Bit Verification
RT3, RT5, and RT7 Samples
Start Bit Verification
Noise Flag
000
Yes
0
001
Yes
1
010
Yes
1
011
No
0
100
Yes
1
101
No
0
110
No
0
111
No
0
RESET RT CLOCK
RT1
RT2
RT3
RT4
RT5
RT8
RT7
RT6
RT
11
RT
10
RT9
RT
15
RT
14
RT
13
RT
12
RT
16
RT1
RT2
RT3
RT4
SAMPLES
RT CLOCK
RT CLOCK COUNT
START BIT
RXD
START BIT
QUALIFICATION
START BIT
DATA
SAMPLING
11
1
11
0
00
LSB
VERIFICATION